From 86e37fbe0139c481473c4204224d0ee0482947b1 Mon Sep 17 00:00:00 2001 From: Victor Sun Date: Sat, 10 Oct 2020 11:43:10 +0800 Subject: [PATCH] HV: add config code for cfl-k700-i7 board Add configurations code of industry scenario and hybrid_rt scenario for cfl-k700-i7 board to support build acrn binary from source code directly. Tracked-On: #5212 Signed-off-by: Victor Sun --- misc/vm_configs/boards/cfl-k700-i7/board.c | 108 ++++++++++++ .../boards/cfl-k700-i7/board_info.h | 18 ++ .../boards/cfl-k700-i7/pci_devices.h | 95 +++++++++++ .../boards/cfl-k700-i7/platform_acpi_info.h | 77 +++++++++ .../hybrid_rt/cfl-k700-i7/VM0/apic.asl | 54 ++++++ .../hybrid_rt/cfl-k700-i7/VM0/dsdt.asl | 32 ++++ .../hybrid_rt/cfl-k700-i7/VM0/facp.asl | 157 ++++++++++++++++++ .../hybrid_rt/cfl-k700-i7/VM0/mcfg.asl | 27 +++ .../hybrid_rt/cfl-k700-i7/VM0/rsdp.asl | 16 ++ .../hybrid_rt/cfl-k700-i7/VM0/tpm2.asl | 23 +++ .../hybrid_rt/cfl-k700-i7/VM0/xsdt.asl | 24 +++ .../hybrid_rt/cfl-k700-i7/cfl-k700-i7.config | 38 +++++ .../hybrid_rt/cfl-k700-i7/ivshmem_cfg.h | 28 ++++ .../hybrid_rt/cfl-k700-i7/misc_cfg.h | 64 +++++++ .../scenarios/hybrid_rt/cfl-k700-i7/pci_dev.c | 57 +++++++ .../scenarios/hybrid_rt/cfl-k700-i7/pt_intx.c | 10 ++ .../hybrid_rt/cfl-k700-i7/vbar_base.h | 70 ++++++++ .../scenarios/hybrid_rt/vm_configurations.h | 2 +- .../industry/cfl-k700-i7/cfl-k700-i7.config | 38 +++++ .../industry/cfl-k700-i7/ivshmem_cfg.h | 9 + .../scenarios/industry/cfl-k700-i7/misc_cfg.h | 66 ++++++++ .../scenarios/industry/cfl-k700-i7/pci_dev.c | 12 ++ .../scenarios/industry/cfl-k700-i7/pt_intx.c | 10 ++ .../industry/cfl-k700-i7/vbar_base.h | 10 ++ 24 files changed, 1044 insertions(+), 1 deletion(-) create mode 100644 misc/vm_configs/boards/cfl-k700-i7/board.c create mode 100644 misc/vm_configs/boards/cfl-k700-i7/board_info.h create mode 100644 misc/vm_configs/boards/cfl-k700-i7/pci_devices.h create mode 100644 misc/vm_configs/boards/cfl-k700-i7/platform_acpi_info.h create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/apic.asl create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/dsdt.asl create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/facp.asl create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/mcfg.asl create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/rsdp.asl create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/tpm2.asl create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/xsdt.asl create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/cfl-k700-i7.config create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/ivshmem_cfg.h create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/misc_cfg.h create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/pci_dev.c create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/pt_intx.c create mode 100644 misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/vbar_base.h create mode 100644 misc/vm_configs/scenarios/industry/cfl-k700-i7/cfl-k700-i7.config create mode 100644 misc/vm_configs/scenarios/industry/cfl-k700-i7/ivshmem_cfg.h create mode 100644 misc/vm_configs/scenarios/industry/cfl-k700-i7/misc_cfg.h create mode 100644 misc/vm_configs/scenarios/industry/cfl-k700-i7/pci_dev.c create mode 100644 misc/vm_configs/scenarios/industry/cfl-k700-i7/pt_intx.c create mode 100644 misc/vm_configs/scenarios/industry/cfl-k700-i7/vbar_base.h diff --git a/misc/vm_configs/boards/cfl-k700-i7/board.c b/misc/vm_configs/boards/cfl-k700-i7/board.c new file mode 100644 index 000000000..8d7673e94 --- /dev/null +++ b/misc/vm_configs/boards/cfl-k700-i7/board.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * BIOS Information + * Vendor: INSYDE Corp. + * Version: Z01-0001A027 + * Release Date: 10/14/2019 + * BIOS Revision: 1.28 + * + * Base Board Information + * Manufacturer: Logic Supply + * Product Name: RXM-181 + * Version: Type2 - Board Version + */ + +#include +#include +#include +#include +#include + +static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = { + { + .type = DRHD0_DEVSCOPE0_TYPE, + .id = DRHD0_DEVSCOPE0_ID, + .bus = DRHD0_DEVSCOPE0_BUS, + .devfun = DRHD0_DEVSCOPE0_PATH, + }, +}; + +static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = { + { + .type = DRHD1_DEVSCOPE0_TYPE, + .id = DRHD1_DEVSCOPE0_ID, + .bus = DRHD1_DEVSCOPE0_BUS, + .devfun = DRHD1_DEVSCOPE0_PATH, + }, + { + .type = DRHD1_DEVSCOPE1_TYPE, + .id = DRHD1_DEVSCOPE1_ID, + .bus = DRHD1_DEVSCOPE1_BUS, + .devfun = DRHD1_DEVSCOPE1_PATH, + }, +}; + +static struct dmar_drhd drhd_info_array[DRHD_COUNT] = { + { + .dev_cnt = DRHD0_DEV_CNT, + .segment = DRHD0_SEGMENT, + .flags = DRHD0_FLAGS, + .reg_base_addr = DRHD0_REG_BASE, + .ignore = DRHD0_IGNORE, + .devices = drhd0_dev_scope + }, + { + .dev_cnt = DRHD1_DEV_CNT, + .segment = DRHD1_SEGMENT, + .flags = DRHD1_FLAGS, + .reg_base_addr = DRHD1_REG_BASE, + .ignore = DRHD1_IGNORE, + .devices = drhd1_dev_scope + }, +}; + +struct dmar_info plat_dmar_info = { + .drhd_count = DRHD_COUNT, + .drhd_units = drhd_info_array, +}; + +#ifdef CONFIG_RDT_ENABLED +struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES]; +struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES]; +struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES]; +#endif + +static const struct cpu_cx_data board_cpu_cx[3] = { + {{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */ + {{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1816UL}, 0x02U, 0x97U, 0x00U}, /* C2 */ + {{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1819UL}, 0x03U, 0x40AU, 0x00U}, /* C3 */ +}; + +static const struct cpu_px_data board_cpu_px[12] = { + {0x709UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002600UL, 0x002600UL}, /* P0 */ + {0x708UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001200UL, 0x001200UL}, /* P1 */ + {0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL}, /* P2 */ + {0x640UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001000UL, 0x001000UL}, /* P3 */ + {0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P4 */ + {0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL}, /* P5 */ + {0x514UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000D00UL, 0x000D00UL}, /* P6 */ + {0x4B0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000C00UL, 0x000C00UL}, /* P7 */ + {0x44CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000B00UL, 0x000B00UL}, /* P8 */ + {0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P9 */ + {0x384UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000900UL, 0x000900UL}, /* P10 */ + {0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P11 */ +}; + +const struct cpu_state_table board_cpu_state_tbl = { + "Intel(R) Core(TM) i7-9700TE CPU @ 1.80GHz", + {(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px, + (uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx} +}; +const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM]; + +const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM]; diff --git a/misc/vm_configs/boards/cfl-k700-i7/board_info.h b/misc/vm_configs/boards/cfl-k700-i7/board_info.h new file mode 100644 index 000000000..717df138e --- /dev/null +++ b/misc/vm_configs/boards/cfl-k700-i7/board_info.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOARD_INFO_H +#define BOARD_INFO_H + +#define MAX_PCPU_NUM 8U +#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U +#define MAX_HIDDEN_PDEVS_NUM 0U + +#define HI_MMIO_START ~0UL +#define HI_MMIO_END 0UL +#define HI_MMIO_SIZE 0x0UL + +#endif /* BOARD_INFO_H */ diff --git a/misc/vm_configs/boards/cfl-k700-i7/pci_devices.h b/misc/vm_configs/boards/cfl-k700-i7/pci_devices.h new file mode 100644 index 000000000..cdb4bb330 --- /dev/null +++ b/misc/vm_configs/boards/cfl-k700-i7/pci_devices.h @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * BIOS Information + * Vendor: INSYDE Corp. + * Version: Z01-0001A027 + * Release Date: 10/14/2019 + * BIOS Revision: 1.28 + * + * Base Board Information + * Manufacturer: Logic Supply + * Product Name: RXM-181 + * Version: Type2 - Board Version + */ + +#ifndef PCI_DEVICES_H_ +#define PCI_DEVICES_H_ + +#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U} + +#define VGA_COMPATIBLE_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U} + +#define SYSTEM_PERIPHERAL_0 .pbdf.bits = {.b = 0x00U, .d = 0x08U, .f = 0x00U} + +#define SIGNAL_PROCESSING_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x00U} + +#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U} + +#define RAM_MEMORY_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U} + +#define SERIAL_BUS_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x00U} + +#define SERIAL_BUS_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x01U} + +#define SERIAL_BUS_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x05U} + +#define COMMUNICATION_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U} + +#define COMMUNICATION_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x00U} + +#define SERIAL_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x03U} + +#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U} + +#define PCI_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x00U} + +#define PCI_BRIDGE_1 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x06U} + +#define PCI_BRIDGE_2 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x00U} + +#define PCI_BRIDGE_3 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x06U} + +#define PCI_BRIDGE_4 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x07U} + +#define PCI_BRIDGE_5 .pbdf.bits = {.b = 0x02U, .d = 0x00U, .f = 0x00U} + +#define PCI_BRIDGE_6 .pbdf.bits = {.b = 0x03U, .d = 0x01U, .f = 0x00U} + +#define PCI_BRIDGE_7 .pbdf.bits = {.b = 0x03U, .d = 0x02U, .f = 0x00U} + +#define PCI_BRIDGE_8 .pbdf.bits = {.b = 0x03U, .d = 0x03U, .f = 0x00U} + +#define PCI_BRIDGE_9 .pbdf.bits = {.b = 0x03U, .d = 0x04U, .f = 0x00U} + +#define PCI_BRIDGE_10 .pbdf.bits = {.b = 0x03U, .d = 0x05U, .f = 0x00U} + +#define ISA_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x00U} + +#define AUDIO_DEVICE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x03U} + +#define SMBUS_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x04U} + +#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x06U} + +#define ETHERNET_CONTROLLER_1 .pbdf.bits = {.b = 0x04U, .d = 0x00U, .f = 0x00U} + +#define ETHERNET_CONTROLLER_2 .pbdf.bits = {.b = 0x05U, .d = 0x00U, .f = 0x00U} + +#define ETHERNET_CONTROLLER_3 .pbdf.bits = {.b = 0x06U, .d = 0x00U, .f = 0x00U} + +#define ETHERNET_CONTROLLER_4 .pbdf.bits = {.b = 0x07U, .d = 0x00U, .f = 0x00U} + +#define ETHERNET_CONTROLLER_5 .pbdf.bits = {.b = 0x0AU, .d = 0x00U, .f = 0x00U} + +#define ETHERNET_CONTROLLER_6 .pbdf.bits = {.b = 0x0BU, .d = 0x00U, .f = 0x00U} + +#define NON_VOLATILE_MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x01U, .d = 0x00U, .f = 0x00U} + +#define NON_VOLATILE_MEMORY_CONTROLLER_1 .pbdf.bits = {.b = 0x09U, .d = 0x00U, .f = 0x00U} + +#endif /* PCI_DEVICES_H_ */ diff --git a/misc/vm_configs/boards/cfl-k700-i7/platform_acpi_info.h b/misc/vm_configs/boards/cfl-k700-i7/platform_acpi_info.h new file mode 100644 index 000000000..018f47b5a --- /dev/null +++ b/misc/vm_configs/boards/cfl-k700-i7/platform_acpi_info.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* DO NOT MODIFY THIS FILE UNLESS YOU KNOW WHAT YOU ARE DOING! + */ + +#ifndef PLATFORM_ACPI_INFO_H +#define PLATFORM_ACPI_INFO_H + +/* + * BIOS Information + * Vendor: INSYDE Corp. + * Version: Z01-0001A027 + * Release Date: 10/14/2019 + * BIOS Revision: 1.28 + * + * Base Board Information + * Manufacturer: Logic Supply + * Product Name: RXM-181 + * Version: Type2 - Board Version + */ + +/* pm sstate data */ +#define PM1A_EVT_ADDRESS 0x1800UL +#define PM1A_EVT_ACCESS_SIZE 0x2U +#undef PM1B_EVT_SPACE_ID +#define PM1B_EVT_SPACE_ID SPACE_SYSTEM_MEMORY +#define PM1A_CNT_ADDRESS 0x1804UL +#undef PM1B_CNT_SPACE_ID +#define PM1B_CNT_SPACE_ID SPACE_SYSTEM_MEMORY + +#define WAKE_VECTOR_32 0x8BB2F00CUL +#define WAKE_VECTOR_64 0x8BB2F018UL + +#define RESET_REGISTER_ADDRESS 0xB2UL +#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO +#define RESET_REGISTER_VALUE 0xfbU + +/* DRHD of DMAR */ +#define DRHD_COUNT 2U + +#define DRHD0_DEV_CNT 0x1U +#define DRHD0_SEGMENT 0x0U +#define DRHD0_FLAGS 0x0U +#define DRHD0_REG_BASE 0xFED90000UL +#define DRHD0_IGNORE true +#define DRHD0_DEVSCOPE0_TYPE 0x1U +#define DRHD0_DEVSCOPE0_ID 0x0U +#define DRHD0_DEVSCOPE0_BUS 0x0U +#define DRHD0_DEVSCOPE0_PATH 0x10U + +#define DRHD1_DEV_CNT 0x2U +#define DRHD1_SEGMENT 0x0U +#define DRHD1_FLAGS 0x1U +#define DRHD1_REG_BASE 0xFED91000UL +#define DRHD1_IGNORE false +#define DRHD1_DEVSCOPE0_TYPE 0x3U +#define DRHD1_DEVSCOPE0_ID 0x2U +#define DRHD1_DEVSCOPE0_BUS 0x0U +#define DRHD1_DEVSCOPE0_PATH 0xf7U +#define DRHD1_DEVSCOPE1_TYPE 0x4U +#define DRHD1_DEVSCOPE1_ID 0x0U +#define DRHD1_DEVSCOPE1_BUS 0x0U +#define DRHD1_DEVSCOPE1_PATH 0xf6U + +/* PCI mmcfg base of MCFG */ +#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL + +/* PCI mmcfg bus number of MCFG */ +#define DEFAULT_PCI_MMCFG_START_BUS 0x0U +#define DEFAULT_PCI_MMCFG_END_BUS 0xFFU + + +#endif /* PLATFORM_ACPI_INFO_H */ diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/apic.asl b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/apic.asl new file mode 100644 index 000000000..84bb878fd --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/apic.asl @@ -0,0 +1,54 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[0004] Table Length : 0000004E +[0001] Revision : 03 +[0001] Checksum : 9B +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNMADT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] Local Apic Address : FEE00000 +[0004] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[0001] Subtable Type : 01 [I/O APIC] +[0001] Length : 0C +[0001] I/O Apic ID : 01 +[0001] Reserved : 00 +[0004] Address : FEC00000 +[0004] Interrupt : 00000000 + +[0001] Subtable Type : 04 [Local APIC NMI] +[0001] Length : 06 +[0001] Processor ID : FF +[0002] Flags (decoded below) : 0005 + Polarity : 1 + Trigger Mode : 1 +[0001] Interrupt Input LINT : 01 + +[0001] Subtable Type : 00 [Processor Local APIC] +[0001] Length : 08 +[0001] Processor ID : 00 +[0001] Local Apic ID : 00 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[0001] Subtable Type : 00 [Processor Local APIC] +[0001] Length : 08 +[0001] Processor ID : 01 +[0001] Local Apic ID : 01 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/dsdt.asl b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/dsdt.asl new file mode 100644 index 000000000..73bf2a93d --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/dsdt.asl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00000051 (81) + * Revision 0x03 + * Checksum 0xF0 + * OEM ID "ACRN " + * OEM Table ID "ACRNDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "INTL" + * Compiler Version 0x20190703 (538511107) + */ +DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001) +{ + Device (TPM) + { + Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + ) + }) + } + +} + diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/facp.asl b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/facp.asl new file mode 100644 index 000000000..34d4ead1b --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/facp.asl @@ -0,0 +1,157 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[0004] Table Length : 000000F4 +[0001] Revision : 03 +[0001] Checksum : 28 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNFADT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] FACS Address : 00000000 +[0004] DSDT Address : 7FF00200 +[0001] Model : 00 +[0001] PM Profile : 00 [Unspecified] +[0002] SCI Interrupt : 0000 +[0004] SMI Command Port : 00000000 +[0001] ACPI Enable Value : 00 +[0001] ACPI Disable Value : 00 +[0001] S4BIOS Command : 00 +[0001] P-State Control : 00 +[0004] PM1A Event Block Address : 00001800 +[0004] PM1B Event Block Address : 00000000 +[0004] PM1A Control Block Address : 00001804 +[0004] PM1B Control Block Address : 00000000 +[0004] PM2 Control Block Address : 00000000 +[0004] PM Timer Block Address : 00000000 +[0004] GPE0 Block Address : 00000000 +[0004] GPE1 Block Address : 00000000 +[0001] PM1 Event Block Length : 04 +[0001] PM1 Control Block Length : 02 +[0001] PM2 Control Block Length : 00 +[0001] PM Timer Block Length : 00 +[0001] GPE0 Block Length : 00 +[0001] GPE1 Block Length : 00 +[0001] GPE1 Base Offset : 00 +[0001] _CST Support : 00 +[0002] C2 Latency : 0000 +[0002] C3 Latency : 0000 +[0002] CPU Cache Size : 0000 +[0002] Cache Flush Stride : 0000 +[0001] Duty Cycle Offset : 00 +[0001] Duty Cycle Width : 00 +[0001] RTC Day Alarm Index : 00 +[0001] RTC Month Alarm Index : 00 +[0001] RTC Century Index : 00 +[0002] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[0001] Reserved : 00 +[0004] Flags (decoded below) : 00001125 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 1 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 1 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 +Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[0012] Reset Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0001] Value to cause reset : 00 +[0002] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[0001] FADT Minor Revision : 00 +[0008] FACS Address : 0000000000000000 +[0008] DSDT Address : 0000000000000000 +[0012] PM1A Event Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1B Event Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1A Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1B Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM2 Control Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM Timer Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] GPE0 Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] GPE1 Block : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/mcfg.asl b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/mcfg.asl new file mode 100644 index 000000000..1d4de63bc --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/mcfg.asl @@ -0,0 +1,27 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "MCFG" [Memory Mapped Configuration table] +[0004] Table Length : 0000003C +[0001] Revision : 03 +[0001] Checksum : A5 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNMCFG" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0008] Reserved : 0000000000000000 + +[0008] Base Address : 00000000E0000000 +[0002] Segment Group Number : 0000 +[0001] Start Bus Number : 00 +[0001] End Bus Number : FF +[0004] Reserved : 00000000 diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/rsdp.asl b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/rsdp.asl new file mode 100644 index 000000000..0dacd86e9 --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/rsdp.asl @@ -0,0 +1,16 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Template for [RSDP] ACPI Table (AML byte code table) + */ +[0008] Signature : "RSD PTR " +[0001] Checksum : 43 +[0006] Oem ID : "ACRN " +[0001] Revision : 02 +[0004] RSDT Address : 0000000000000000 +[0004] Length : 00000024 +[0008] XSDT Address : 000000007FF00080 +[0001] Extended Checksum : DC +[0003] Reserved : 000000 diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/tpm2.asl b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/tpm2.asl new file mode 100644 index 000000000..2a2a08fc8 --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/tpm2.asl @@ -0,0 +1,23 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [TPM2] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "TPM2" [Trusted Platform Module hardware interface table] +[0004] Table Length : 00000034 +[0001] Revision : 03 +[0001] Checksum : 67 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNTPM2" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0004] Reserved : 00000000 +[0008] Control Address : 00000000FED40040 +[0004] Start Method : 07 diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/xsdt.asl b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/xsdt.asl new file mode 100644 index 000000000..65e79728e --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/VM0/xsdt.asl @@ -0,0 +1,24 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190703 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * ACPI Data Table [XSDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[0004] Signature : "XSDT" [Extended System Description Table] +[0004] Table Length : 00000044 +[0001] Revision : 01 +[0001] Checksum : 75 +[0006] Oem ID : "ACRN " +[0008] Oem Table ID : "ACRNXSDT" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20190703 + +[0008] ACPI Table Address 0 : 000000007FF00100 +[0008] ACPI Table Address 1 : 000000007FF00400 +[0008] ACPI Table Address 2 : 000000007FF00440 +[0008] ACPI Table Address 3 : 000000007FF01100 diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/cfl-k700-i7.config b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/cfl-k700-i7.config new file mode 100644 index 000000000..654c82813 --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/cfl-k700-i7.config @@ -0,0 +1,38 @@ +# Board defconfig generated by acrn-config tool + +CONFIG_BOARD="cfl-k700-i7" +CONFIG_HV_RAM_START=0x11000000 +CONFIG_HV_RAM_SIZE=0x9800000 +CONFIG_PLATFORM_RAM_SIZE=0x800000000 +CONFIG_LOW_RAM_SIZE=0x00010000 +CONFIG_SOS_RAM_SIZE=0x800000000 +CONFIG_UOS_RAM_SIZE=0x200000000 +CONFIG_STACK_SIZE=0x2000 +CONFIG_IVSHMEM_ENABLED=y +CONFIG_GPU_SBDF=0x00000010 +CONFIG_UEFI_OS_LOADER_NAME="" +CONFIG_SCHED_BVT=y +CONFIG_RELOC=y +CONFIG_MULTIBOOT2=y +CONFIG_RDT_ENABLED=n +CONFIG_CDP_ENABLED=n +CONFIG_HYPERV_ENABLED=y +CONFIG_IOMMU_ENFORCE_SNP=n +CONFIG_ACPI_PARSE_ENABLED=y +CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n +CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n +CONFIG_IOMMU_BUS_NUM=0x100 +CONFIG_MAX_IOAPIC_NUM=1 +CONFIG_MAX_IR_ENTRIES=256 +CONFIG_MAX_PCI_DEV_NUM=96 +CONFIG_MAX_IOAPIC_LINES=120 +CONFIG_MAX_PT_IRQ_ENTRIES=64 +CONFIG_MAX_MSIX_TABLE_NUM=64 +CONFIG_MAX_EMULATED_MMIO_REGIONS=16 +CONFIG_SERIAL_LEGACY=y +CONFIG_SERIAL_PIO_BASE=0x3F8 +CONFIG_LOG_BUF_SIZE=0x40000 +CONFIG_NPK_LOGLEVEL_DEFAULT=5 +CONFIG_MEM_LOGLEVEL_DEFAULT=5 +CONFIG_LOG_DESTINATION=7 +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3 diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/ivshmem_cfg.h b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/ivshmem_cfg.h new file mode 100644 index 000000000..3104f28d8 --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/ivshmem_cfg.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef IVSHMEM_CFG_H +#define IVSHMEM_CFG_H + +#include +#include + +#define IVSHMEM_SHM_REGION_0 "hv:/shm_region_0" + +/* + * The IVSHMEM_SHM_SIZE is the sum of all memory regions. + * The size range of each memory region is [2MB, 512MB] and is a power of 2. + */ +#define IVSHMEM_SHM_SIZE 0x200000UL +#define IVSHMEM_DEV_NUM 2UL + +/* All user defined memory regions */ +#define IVSHMEM_SHM_REGIONS \ + { \ + .name = IVSHMEM_SHM_REGION_0, \ + .size = 0x200000UL, /* 2M */ \ + }, + +#endif /* IVSHMEM_CFG_H */ diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/misc_cfg.h b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/misc_cfg.h new file mode 100644 index 000000000..ccdb46d08 --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/misc_cfg.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MISC_CFG_H +#define MISC_CFG_H + +#define SOS_ROOTFS "root=/dev/nvme0n1p3 " +#define SOS_CONSOLE "console=ttyS0 " +#define SOS_COM1_BASE 0x3F8U +#define SOS_COM1_IRQ 4U +#define SOS_COM2_BASE 0x2F8U +#define SOS_COM2_IRQ 3U + +#define SOS_BOOTARGS_DIFF "rw " \ + "rootwait " \ + "console=ttyS0,115200n8 " \ + "ignore_loglevel " \ + "no_timer_check " \ + "hvlog=2M@0xe00000 " \ + "memmap=0x200000$0xe00000 " \ + "maxcpus=2" + +#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U)) + +#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U)) + +#ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ +#define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ +#define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ +#define MAX_CACHE_CLOS_NUM_ENTRIES 0U +#endif + +#define VM0_CONFIG_PCI_DEV_NUM 4U +#define VM2_CONFIG_PCI_DEV_NUM 1U + +#define VM0_BOOT_ARGS "rw rootwait root=/dev/nvme0n1p2 earlyprintk=serial,ttyS0,115200 \ +console=ttyS0,115200n8 log_buf_len=2M ignore_loglevel noxsave \ +nohpet no_timer_check tsc=reliable" + + +#define VM0_PT_INTX_NUM 0U + +#endif /* MISC_CFG_H */ diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/pci_dev.c b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/pci_dev.c new file mode 100644 index 000000000..fce9cd9c1 --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/pci_dev.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * TODO: remove PTDEV macro and add DEV_PRIVINFO macro to initialize pbdf for + * passthrough device configuration and shm_name for ivshmem device configuration. + */ +#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR + +/* + * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops + * to simplify the code. + */ +struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = { + { + .emu_type = PCI_DEV_TYPE_HVEMUL, + .vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}, + .vdev_ops = &vhostbridge_ops, + }, + { + .emu_type = PCI_DEV_TYPE_PTDEV, + .vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U}, + PTDEV(ETHERNET_CONTROLLER_0), + }, + { + .emu_type = PCI_DEV_TYPE_PTDEV, + .vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}, + PTDEV(NON_VOLATILE_MEMORY_CONTROLLER_0), + }, + { + .emu_type = PCI_DEV_TYPE_HVEMUL, + .vbdf.bits = {.b = 0x00U, .d = 0x03U, .f = 0x00U}, + .vdev_ops = &vpci_ivshmem_ops, + .shm_region_name = IVSHMEM_SHM_REGION_0, + IVSHMEM_DEVICE_0_VBAR + }, +}; + +struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM] = { + { + .emu_type = PCI_DEV_TYPE_HVEMUL, + .vbdf.value = UNASSIGNED_VBDF, + .vdev_ops = &vpci_ivshmem_ops, + .shm_region_name = IVSHMEM_SHM_REGION_0 + }, +}; diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/pt_intx.c b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/pt_intx.c new file mode 100644 index 000000000..7573f370e --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/pt_intx.c @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +struct pt_intx_config vm0_pt_intx[1U]; + diff --git a/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/vbar_base.h b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/vbar_base.h new file mode 100644 index 000000000..3cb6a4712 --- /dev/null +++ b/misc/vm_configs/scenarios/hybrid_rt/cfl-k700-i7/vbar_base.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VBAR_BASE_H_ +#define VBAR_BASE_H_ + +#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0xa0000000UL, \ + .vbar_base[2] = 0x90000000UL + +#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0xa1938000UL + +#define SIGNAL_PROCESSING_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1939000UL + +#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1920000UL + +#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0xa1934000UL, \ + .vbar_base[2] = 0xa193a000UL + +#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x8f800000UL + +#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x8f801000UL + +#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0xfe010000UL + +#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0xa193d000UL + +#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x8f802000UL + +#define SERIAL_CONTROLLER_0_VBAR .vbar_base[1] = 0xa1943000UL + +#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1936000UL, \ + .vbar_base[1] = 0xa1942000UL, \ + .vbar_base[5] = 0xa1941000UL + +#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = 0xa1930000UL, \ + .vbar_base[4] = 0xa1000000UL + +#define SMBUS_0_VBAR .vbar_base[0] = 0xa193f000UL + +#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1900000UL + +#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0xa1700000UL, \ + .vbar_base[3] = 0xa1780000UL + +#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0xa1600000UL, \ + .vbar_base[3] = 0xa1680000UL + +#define ETHERNET_CONTROLLER_3_VBAR .vbar_base[0] = 0xa1500000UL, \ + .vbar_base[3] = 0xa1580000UL + +#define ETHERNET_CONTROLLER_4_VBAR .vbar_base[0] = 0xa1400000UL, \ + .vbar_base[3] = 0xa1480000UL + +#define ETHERNET_CONTROLLER_5_VBAR .vbar_base[0] = 0xa1200000UL, \ + .vbar_base[3] = 0xa1280000UL + +#define ETHERNET_CONTROLLER_6_VBAR .vbar_base[0] = 0xa1100000UL, \ + .vbar_base[3] = 0xa1180000UL + +#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0xa1800000UL + +#define NON_VOLATILE_MEMORY_CONTROLLER_1_VBAR .vbar_base[0] = 0xa1300000UL + +#define IVSHMEM_DEVICE_0_VBAR .vbar_base[0] = 0x80000000UL, \ + .vbar_base[2] = 0x10000000cUL + +#endif /* VBAR_BASE_H_ */ diff --git a/misc/vm_configs/scenarios/hybrid_rt/vm_configurations.h b/misc/vm_configs/scenarios/hybrid_rt/vm_configurations.h index a177a9ae6..f2363ffd1 100644 --- a/misc/vm_configs/scenarios/hybrid_rt/vm_configurations.h +++ b/misc/vm_configs/scenarios/hybrid_rt/vm_configurations.h @@ -23,7 +23,7 @@ GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING) #define VM0_CONFIG_MEM_START_HPA 0x100000000UL -#define VM0_CONFIG_MEM_SIZE 0xC0000000UL +#define VM0_CONFIG_MEM_SIZE 0x40000000UL #define VM0_CONFIG_MEM_START_HPA2 0x0UL #define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL diff --git a/misc/vm_configs/scenarios/industry/cfl-k700-i7/cfl-k700-i7.config b/misc/vm_configs/scenarios/industry/cfl-k700-i7/cfl-k700-i7.config new file mode 100644 index 000000000..a0466295d --- /dev/null +++ b/misc/vm_configs/scenarios/industry/cfl-k700-i7/cfl-k700-i7.config @@ -0,0 +1,38 @@ +# Board defconfig generated by acrn-config tool + +CONFIG_BOARD="cfl-k700-i7" +CONFIG_HV_RAM_START=0x11000000 +CONFIG_HV_RAM_SIZE=0x16800000 +CONFIG_PLATFORM_RAM_SIZE=0x800000000 +CONFIG_LOW_RAM_SIZE=0x00010000 +CONFIG_SOS_RAM_SIZE=0x800000000 +CONFIG_UOS_RAM_SIZE=0x200000000 +CONFIG_STACK_SIZE=0x2000 +CONFIG_IVSHMEM_ENABLED=n +CONFIG_GPU_SBDF=0x00000010 +CONFIG_UEFI_OS_LOADER_NAME="\\EFI\\BOOT\\bootx64.efi" +CONFIG_SCHED_BVT=y +CONFIG_RELOC=y +CONFIG_MULTIBOOT2=y +CONFIG_RDT_ENABLED=n +CONFIG_CDP_ENABLED=n +CONFIG_HYPERV_ENABLED=y +CONFIG_IOMMU_ENFORCE_SNP=n +CONFIG_ACPI_PARSE_ENABLED=y +CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n +CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n +CONFIG_IOMMU_BUS_NUM=0x100 +CONFIG_MAX_IOAPIC_NUM=1 +CONFIG_MAX_IR_ENTRIES=256 +CONFIG_MAX_PCI_DEV_NUM=96 +CONFIG_MAX_IOAPIC_LINES=120 +CONFIG_MAX_PT_IRQ_ENTRIES=64 +CONFIG_MAX_MSIX_TABLE_NUM=64 +CONFIG_MAX_EMULATED_MMIO_REGIONS=16 +CONFIG_SERIAL_LEGACY=y +CONFIG_SERIAL_PIO_BASE=0x3F8 +CONFIG_LOG_BUF_SIZE=0x40000 +CONFIG_NPK_LOGLEVEL_DEFAULT=5 +CONFIG_MEM_LOGLEVEL_DEFAULT=5 +CONFIG_LOG_DESTINATION=7 +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3 diff --git a/misc/vm_configs/scenarios/industry/cfl-k700-i7/ivshmem_cfg.h b/misc/vm_configs/scenarios/industry/cfl-k700-i7/ivshmem_cfg.h new file mode 100644 index 000000000..3c2ee2d52 --- /dev/null +++ b/misc/vm_configs/scenarios/industry/cfl-k700-i7/ivshmem_cfg.h @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef IVSHMEM_CFG_H +#define IVSHMEM_CFG_H + +#endif /* IVSHMEM_CFG_H */ diff --git a/misc/vm_configs/scenarios/industry/cfl-k700-i7/misc_cfg.h b/misc/vm_configs/scenarios/industry/cfl-k700-i7/misc_cfg.h new file mode 100644 index 000000000..eae3fafa1 --- /dev/null +++ b/misc/vm_configs/scenarios/industry/cfl-k700-i7/misc_cfg.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MISC_CFG_H +#define MISC_CFG_H + +#define SOS_ROOTFS "root=/dev/sda3 " +#define SOS_CONSOLE "console=ttyS0 " +#define SOS_COM1_BASE 0x3F8U +#define SOS_COM1_IRQ 4U +#define SOS_COM2_BASE 0x2F8U +#define SOS_COM2_IRQ 3U + +#define SOS_BOOTARGS_DIFF "rw " \ + "rootwait " \ + "console=tty0 " \ + "consoleblank=0 " \ + "no_timer_check " \ + "quiet " \ + "loglevel=3 " \ + "i915.nuclear_pageflip=1 " \ + "hvlog=2M@0xe00000 " \ + "memmap=0x200000$0xe00000 " \ + "maxcpus=8" + + +#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U) | AFFINITY_CPU(4U) | AFFINITY_CPU(5U) | AFFINITY_CPU(6U) | AFFINITY_CPU(7U)) +#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U)) +#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM4_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM5_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM6_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) +#define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U)) + +#ifdef CONFIG_RDT_ENABLED + +/* + * The maximum CLOS that is allowed by ACRN hypervisor, + * its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0]) + * among all supported RDT resources in the platform. In other words, it is + * min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent + * CLOS allocations between all the RDT resources. + */ +#define HV_SUPPORTED_MAX_CLOS 0U + +/* + * Max number of Cache Mask entries corresponding to each CLOS. + * This can vary if CDP is enabled vs disabled, as each CLOS entry + * will have corresponding cache mask values for Data and Code when + * CDP is enabled. + */ +#define MAX_MBA_CLOS_NUM_ENTRIES 0U + +/* Max number of MBA delay entries corresponding to each CLOS. */ +#define MAX_CACHE_CLOS_NUM_ENTRIES 0U +#endif + + + +#define VM0_PT_INTX_NUM 0U + +#endif /* MISC_CFG_H */ diff --git a/misc/vm_configs/scenarios/industry/cfl-k700-i7/pci_dev.c b/misc/vm_configs/scenarios/industry/cfl-k700-i7/pci_dev.c new file mode 100644 index 000000000..79033ec6b --- /dev/null +++ b/misc/vm_configs/scenarios/industry/cfl-k700-i7/pci_dev.c @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include diff --git a/misc/vm_configs/scenarios/industry/cfl-k700-i7/pt_intx.c b/misc/vm_configs/scenarios/industry/cfl-k700-i7/pt_intx.c new file mode 100644 index 000000000..7573f370e --- /dev/null +++ b/misc/vm_configs/scenarios/industry/cfl-k700-i7/pt_intx.c @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +struct pt_intx_config vm0_pt_intx[1U]; + diff --git a/misc/vm_configs/scenarios/industry/cfl-k700-i7/vbar_base.h b/misc/vm_configs/scenarios/industry/cfl-k700-i7/vbar_base.h new file mode 100644 index 000000000..9077629d8 --- /dev/null +++ b/misc/vm_configs/scenarios/industry/cfl-k700-i7/vbar_base.h @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VBAR_BASE_H_ +#define VBAR_BASE_H_ + +#endif /* VBAR_BASE_H_ */