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https://github.com/projectacrn/acrn-hypervisor.git
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HV: vlapic: add suffix 'U' when necessary
For constants used in unsigned contexts, a 'U' suffix is required per MISRA C standard. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Dong Eddie <eddie.dong@intel.com>
This commit is contained in:
Junjie Mao
lijinxia
parent
1af8586cd1
commit
87f2d4c042
@ -39,14 +39,14 @@
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#define VLAPIC_VERBOS 0
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#define PRIO(x) ((x) >> 4)
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#define VLAPIC_VERSION (16)
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#define VLAPIC_VERSION (16U)
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#define APICBASE_RESERVED 0x000002ffU
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#define APICBASE_BSP 0x00000100U
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#define APICBASE_X2APIC 0x00000400U
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#define APICBASE_ENABLED 0x00000800U
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#define ACRN_DBG_LAPIC 6
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#define ACRN_DBG_LAPIC 6U
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#if VLAPIC_VERBOS
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static inline void vlapic_dump_irr(struct vlapic *vlapic, char *msg)
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@ -138,7 +138,7 @@ static uint16_t vm_apicid2vcpu_id(struct vm *vm, uint8_t lapicid)
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static uint64_t
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vm_active_cpus(struct vm *vm)
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{
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uint64_t dmask = 0;
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uint64_t dmask = 0UL;
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uint16_t i;
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struct vcpu *vcpu;
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@ -226,8 +226,8 @@ vlapic_timer_divisor_shift(uint32_t dcr)
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{
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uint32_t val;
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val = ((dcr & 0x3) | ((dcr & 0x8) >> 1));
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return ((val + 1) & 0x7);
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val = ((dcr & 0x3U) | ((dcr & 0x8U) >> 1U));
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return ((val + 1U) & 0x7U);
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}
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static inline bool
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@ -254,7 +254,7 @@ vlapic_lvtt_tsc_deadline(struct vlapic *vlapic)
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static inline bool
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vlapic_lvtt_masked(struct vlapic *vlapic)
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{
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return !!(vlapic->apic_page->lvt[APIC_LVT_TIMER].val & APIC_LVTT_M);
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return (vlapic->apic_page->lvt[APIC_LVT_TIMER].val & APIC_LVTT_M) != 0U;
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}
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static void vlapic_create_timer(struct vlapic *vlapic)
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@ -266,11 +266,11 @@ static void vlapic_create_timer(struct vlapic *vlapic)
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}
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vlapic_timer = &vlapic->vlapic_timer;
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(void)memset(vlapic_timer, 0, sizeof(struct vlapic_timer));
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(void)memset(vlapic_timer, 0U, sizeof(struct vlapic_timer));
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initialize_timer(&vlapic_timer->timer,
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vlapic_timer_expired, vlapic->vcpu,
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0, 0, 0);
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0UL, 0, 0UL);
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}
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static void vlapic_reset_timer(struct vlapic *vlapic)
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@ -342,7 +342,7 @@ static void vlapic_update_lvtt(struct vlapic *vlapic,
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static uint32_t vlapic_get_ccr(struct vlapic *vlapic)
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{
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uint64_t now = rdtsc();
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uint64_t remain_count = 0;
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uint32_t remain_count = 0U;
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struct vlapic_timer *vlapic_timer;
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vlapic_timer = &vlapic->vlapic_timer;
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@ -472,10 +472,11 @@ vlapic_set_intr_ready(struct vlapic *vlapic, uint32_t vector, bool level)
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(vlapic, vector, level);
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idx = vector / 32U;
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mask = 1U << (vector % 32U);
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irrptr = &lapic->irr[0];
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/* If the interrupt is set, don't try to do it again */
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if (bitmap32_test_and_set((vector % 32U), &irrptr[idx].val)) {
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if (bitmap32_test_and_set((uint16_t)(vector % 32U), &irrptr[idx].val)) {
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return 0;
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}
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@ -484,7 +485,7 @@ vlapic_set_intr_ready(struct vlapic *vlapic, uint32_t vector, bool level)
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* the vlapic TMR registers.
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*/
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tmrptr = &lapic->tmr[0];
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if ((tmrptr[idx].val & mask) != (level ? mask : 0)) {
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if ((tmrptr[idx].val & mask) != (level ? mask : 0U)) {
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dev_dbg(ACRN_DBG_LAPIC,
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"vlapic TMR[%d] is 0x%08x but interrupt is %s-triggered",
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idx, tmrptr[idx].val, level ? "level" : "edge");
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@ -602,7 +603,7 @@ vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset)
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uint32_t last = vlapic_get_lvt(vlapic, offset);
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/* mask -> unmask: may from every vlapic in the vm */
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if (((last & APIC_LVT_M) != 0U) && ((val & APIC_LVT_M) == 0)) {
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if (((last & APIC_LVT_M) != 0U) && ((val & APIC_LVT_M) == 0U)) {
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if (vlapic->vm->vpic_wire_mode == VPIC_WIRE_INTR ||
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vlapic->vm->vpic_wire_mode == VPIC_WIRE_NULL) {
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vlapic->vm->vpic_wire_mode = VPIC_WIRE_LAPIC;
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@ -613,7 +614,7 @@ vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset)
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return;
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}
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/* unmask -> mask: only from the vlapic LINT0-ExtINT enabled */
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} else if (((last & APIC_LVT_M) == 0) && ((val & APIC_LVT_M) != 0U)) {
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} else if (((last & APIC_LVT_M) == 0U) && ((val & APIC_LVT_M) != 0U)) {
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if (vlapic->vm->vpic_wire_mode == VPIC_WIRE_LAPIC) {
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vlapic->vm->vpic_wire_mode = VPIC_WIRE_NULL;
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dev_dbg(ACRN_DBG_LAPIC,
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@ -729,8 +730,9 @@ vlapic_update_ppr(struct vlapic *vlapic)
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struct lapic_reg *isrptr;
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uint32_t vector;
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if (vlapic->isrvec_stk_top == 0 && isrvec != 0)
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panic("isrvec_stk is corrupted: %d", isrvec);
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if (vlapic->isrvec_stk_top == 0U && top_isrvec != 0U) {
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panic("isrvec_stk is corrupted: %u", top_isrvec);
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}
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/*
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* Make sure that the priority of the nested interrupts is
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@ -966,7 +968,7 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
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continue;
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}
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if ((mda_ldest & ldest) != 0) {
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if ((mda_ldest & ldest) != 0U) {
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if (lowprio) {
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if (target == NULL) {
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target = vlapic;
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@ -1033,7 +1035,7 @@ vlapic_get_cr8(struct vlapic *vlapic)
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uint8_t tpr;
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tpr = vlapic_get_tpr(vlapic);
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return tpr >> 4;
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return (uint64_t)(tpr >> 4U);
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}
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static int
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@ -1041,7 +1043,7 @@ vlapic_icrlo_write_handler(struct vlapic *vlapic)
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{
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uint16_t vcpu_id;
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bool phys;
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uint64_t dmask = 0;
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uint64_t dmask = 0UL;
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uint64_t icrval;
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uint32_t dest, vec, mode, shorthand;
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struct lapic_regs *lapic;
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@ -1122,11 +1124,11 @@ vlapic_icrlo_write_handler(struct vlapic *vlapic)
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* the second SIPI will be ignored as it move out of
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* wait-for-SIPI state.
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*/
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target_vcpu->arch_vcpu.nr_sipi = 1;
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target_vcpu->arch_vcpu.nr_sipi = 1U;
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} else if (mode == APIC_DELMODE_STARTUP) {
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/* Ignore SIPIs in any state other than wait-for-SIPI */
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if ((target_vcpu->state != VCPU_INIT) ||
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(target_vcpu->arch_vcpu.nr_sipi == 0)) {
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(target_vcpu->arch_vcpu.nr_sipi == 0U)) {
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continue;
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}
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@ -1135,7 +1137,7 @@ vlapic_icrlo_write_handler(struct vlapic *vlapic)
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vlapic->vcpu->vcpu_id, vcpu_id, vec);
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target_vcpu->arch_vcpu.nr_sipi--;
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if (target_vcpu->arch_vcpu.nr_sipi > 0) {
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if (target_vcpu->arch_vcpu.nr_sipi > 0U) {
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continue;
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}
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@ -1199,14 +1201,14 @@ vlapic_intr_accepted(struct vlapic *vlapic, uint32_t vector)
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* clear the ready bit for vector being accepted in irr
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* and set the vector as in service in isr.
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*/
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idx = vector / 32;
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idx = vector / 32U;
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irrptr = &lapic->irr[0];
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atomic_clear_int(&irrptr[idx].val, 1 << (vector % 32));
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atomic_clear_int(&irrptr[idx].val, 1U << (vector % 32U));
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vlapic_dump_irr(vlapic, "vlapic_intr_accepted");
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isrptr = &lapic->isr[0];
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isrptr[idx].val |= 1U << (vector % 32);
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isrptr[idx].val |= 1U << (vector % 32U);
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vlapic_dump_isr(vlapic, "vlapic_intr_accepted");
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/*
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@ -1236,8 +1238,8 @@ vlapic_svr_write_handler(struct vlapic *vlapic)
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vlapic->svr_last = new;
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changed = old ^ new;
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if ((changed & APIC_SVR_ENABLE) != 0) {
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if ((new & APIC_SVR_ENABLE) == 0) {
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if ((changed & APIC_SVR_ENABLE) != 0U) {
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if ((new & APIC_SVR_ENABLE) == 0U) {
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/*
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* The apic is now disabled so stop the apic timer
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* and mask all the LVT entries.
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@ -1527,27 +1529,27 @@ vlapic_reset(struct vlapic *vlapic)
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lapic = vlapic->apic_page;
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apic_page = (void *)vlapic->apic_page;
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(void)memset(apic_page, 0, CPU_PAGE_SIZE);
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(void)memset(apic_page, 0U, CPU_PAGE_SIZE);
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if (vlapic->pir_desc) {
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(void)memset(vlapic->pir_desc, 0, sizeof(struct pir_desc));
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(void)memset(vlapic->pir_desc, 0U, sizeof(struct pir_desc));
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}
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lapic->id = vlapic_build_id(vlapic);
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lapic->version = VLAPIC_VERSION;
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lapic->version |= (VLAPIC_MAXLVT_INDEX << MAXLVTSHIFT);
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lapic->dfr = 0xffffffff;
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lapic->dfr = 0xffffffffU;
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lapic->svr = APIC_SVR_VECTOR;
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vlapic_mask_lvts(vlapic);
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vlapic_reset_tmr(vlapic);
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lapic->icr_timer = 0;
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lapic->dcr_timer = 0;
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lapic->icr_timer = 0U;
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lapic->dcr_timer = 0U;
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vlapic_reset_timer(vlapic);
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vlapic->svr_last = lapic->svr;
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for (i = 0; i < VLAPIC_MAXLVT_INDEX + 1; i++) {
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vlapic->lvt_last[i] = 0;
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for (i = 0U; i < VLAPIC_MAXLVT_INDEX + 1U; i++) {
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vlapic->lvt_last[i] = 0U;
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}
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for (i = 0; i < ISRVEC_STK_SIZE; i++) {
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@ -1694,8 +1696,8 @@ vlapic_set_tmr(struct vlapic *vlapic, uint32_t vector, bool level)
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lapic = vlapic->apic_page;
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tmrptr = &lapic->tmr[0];
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idx = vector / 32;
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mask = 1 << (vector % 32);
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idx = vector / 32U;
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mask = 1U << (vector % 32U);
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if (level) {
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tmrptr[idx].val |= mask;
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} else {
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@ -1731,7 +1733,7 @@ vlapic_reset_tmr(struct vlapic *vlapic)
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dev_dbg(ACRN_DBG_LAPIC,
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"vlapic resetting all vectors to edge-triggered");
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for (vector = 0; vector <= 255; vector++) {
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for (vector = 0U; vector <= 255U; vector++) {
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vlapic_set_tmr(vlapic, vector, false);
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}
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@ -1780,8 +1782,9 @@ vlapic_set_intr(struct vcpu *vcpu, uint32_t vector, bool level)
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* According to section "Maskable Hardware Interrupts" in Intel SDM
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* vectors 16 through 255 can be delivered through the local APIC.
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*/
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if (vector < 16U || vector > 255U)
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if (vector < 16U || vector > 255U) {
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return -EINVAL;
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}
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vlapic = vcpu->arch_vcpu.vlapic;
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if (vlapic_set_intr_ready(vlapic, vector, level) != 0) {
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@ -1797,7 +1800,7 @@ int
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vlapic_set_local_intr(struct vm *vm, uint16_t vcpu_id, uint32_t vector)
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{
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struct vlapic *vlapic;
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uint64_t dmask = 0;
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uint64_t dmask = 0UL;
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int error;
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if ((vcpu_id != BROADCAST_CPU_ID) && (vcpu_id >= phys_cpu_num)) {
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@ -1864,7 +1867,7 @@ vlapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg)
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static bool
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is_x2apic_msr(uint32_t msr)
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{
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if (msr >= 0x800 && msr <= 0xBFF) {
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if (msr >= 0x800U && msr <= 0xBFFU) {
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return true;
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} else {
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return false;
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@ -1874,8 +1877,7 @@ is_x2apic_msr(uint32_t msr)
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static uint32_t
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x2apic_msr_to_regoff(uint32_t msr)
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{
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return (msr - 0x800) << 4;
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return (msr - 0x800U) << 4U;
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}
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bool
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@ -1905,7 +1907,7 @@ static int vlapic_timer_expired(void *data)
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}
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if (!vlapic_lvtt_period(vlapic)) {
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vlapic->vlapic_timer.timer.fire_tsc = 0;
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vlapic->vlapic_timer.timer.fire_tsc = 0UL;
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}
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return 0;
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@ -2022,7 +2024,7 @@ int vlapic_mmio_access_handler(struct vcpu *vcpu, struct mem_io *mmio,
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int ret = 0;
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/* Note all RW to LAPIC are 32-Bit in size */
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ASSERT(mmio->access_size == 4,
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ASSERT(mmio->access_size == 4U,
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"All RW to LAPIC must be 32-bits in size");
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if (mmio->read_write == HV_MEM_IO_READ) {
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@ -2047,12 +2049,12 @@ int vlapic_mmio_access_handler(struct vcpu *vcpu, struct mem_io *mmio,
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int vlapic_create(struct vcpu *vcpu)
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{
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void *apic_page = alloc_page();
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struct vlapic *vlapic = calloc(1, sizeof(struct vlapic));
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struct vlapic *vlapic = calloc(1U, sizeof(struct vlapic));
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ASSERT(vlapic != NULL, "vlapic allocate failed");
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ASSERT(apic_page != NULL, "apic reg page allocate failed");
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(void)memset((void *)apic_page, 0, CPU_PAGE_SIZE);
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(void)memset((void *)apic_page, 0U, CPU_PAGE_SIZE);
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vlapic->vm = vcpu->vm;
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vlapic->vcpu = vcpu;
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vlapic->apic_page = (struct lapic_regs *)apic_page;
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@ -2141,7 +2143,7 @@ apicv_set_intr_ready(struct vlapic *vlapic, uint32_t vector, __unused bool level
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pir_desc = vlapic->pir_desc;
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idx = vector / 64;
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mask = 1UL << (vector % 64);
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mask = 1UL << (vector % 64U);
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atomic_set_long(&pir_desc->pir[idx], mask);
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notify = (atomic_cmpxchg64((long *)&pir_desc->pending, 0, 1) == 0);
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@ -2186,7 +2188,7 @@ apicv_set_tmr(__unused struct vlapic *vlapic, uint32_t vector, bool level)
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{
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uint64_t mask, val;
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mask = 1UL << (vector % 64);
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mask = 1UL << (vector % 64U);
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val = exec_vmread(VMX_EOI_EXIT(vector));
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if (level) {
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@ -2199,19 +2201,19 @@ apicv_set_tmr(__unused struct vlapic *vlapic, uint32_t vector, bool level)
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}
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/* Update the VMX_EOI_EXIT according to related tmr */
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#define EOI_STEP_LEN (64)
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#define TMR_STEP_LEN (32)
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#define EOI_STEP_LEN (64U)
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#define TMR_STEP_LEN (32U)
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static void
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apicv_batch_set_tmr(struct vlapic *vlapic)
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{
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struct lapic_regs *lapic = vlapic->apic_page;
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uint64_t val;
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struct lapic_reg *ptr;
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unsigned int s, e;
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uint32_t s, e;
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ptr = &lapic->tmr[0];
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s = 0;
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e = 256;
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s = 0U;
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e = 256U;
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while (s < e) {
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val = ptr[s/TMR_STEP_LEN + 1].val;
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@ -2234,7 +2236,7 @@ apicv_get_apic_access_addr(__unused struct vm *vm)
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ASSERT(apicv_apic_access_addr != NULL,
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"apicv allocate failed.");
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(void)memset((void *)apicv_apic_access_addr, 0, CPU_PAGE_SIZE);
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(void)memset((void *)apicv_apic_access_addr, 0U, CPU_PAGE_SIZE);
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}
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return HVA2HPA(apicv_apic_access_addr);
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}
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@ -2267,7 +2269,7 @@ apicv_inject_pir(struct vlapic *vlapic)
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if (atomic_cmpxchg64((long *)&pir_desc->pending, 1, 0) != 1)
|
||||
return;
|
||||
|
||||
pirval = 0;
|
||||
pirval = 0UL;
|
||||
lapic = vlapic->apic_page;
|
||||
irr = &lapic->irr[0];
|
||||
|
||||
@ -2303,7 +2305,7 @@ apicv_inject_pir(struct vlapic *vlapic)
|
||||
* (vm exit)
|
||||
* pending bit set, PIR 0
|
||||
*/
|
||||
if (pirval != 0) {
|
||||
if (pirval != 0UL) {
|
||||
rvi = pirbase + fls64(pirval);
|
||||
|
||||
intr_status_old = (uint16_t)
|
||||
@ -2373,15 +2375,15 @@ int veoi_vmexit_handler(struct vcpu *vcpu)
|
||||
vector = (vcpu->arch_vcpu.exit_qualification) & 0xFFUL;
|
||||
|
||||
tmrptr = &lapic->tmr[0];
|
||||
idx = vector / 32;
|
||||
mask = 1 << (vector % 32);
|
||||
idx = vector / 32U;
|
||||
mask = 1U << (vector % 32U);
|
||||
|
||||
if ((tmrptr[idx].val & mask) != 0) {
|
||||
if ((tmrptr[idx].val & mask) != 0U) {
|
||||
/* hook to vIOAPIC */
|
||||
vioapic_process_eoi(vlapic->vm, vector);
|
||||
}
|
||||
|
||||
TRACE_2L(TRACE_VMEXIT_APICV_VIRT_EOI, vector, 0);
|
||||
TRACE_2L(TRACE_VMEXIT_APICV_VIRT_EOI, vector, 0UL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -2444,7 +2446,7 @@ int apic_write_vmexit_handler(struct vcpu *vcpu)
|
||||
break;
|
||||
}
|
||||
|
||||
TRACE_2L(TRACE_VMEXIT_APICV_WRITE, offset, 0);
|
||||
TRACE_2L(TRACE_VMEXIT_APICV_WRITE, offset, 0UL);
|
||||
|
||||
return handled;
|
||||
}
|
||||
|
||||
@ -33,54 +33,54 @@
|
||||
/*
|
||||
* APIC Register: Offset Description
|
||||
*/
|
||||
#define APIC_OFFSET_ID 0x20 /* Local APIC ID */
|
||||
#define APIC_OFFSET_VER 0x30 /* Local APIC Version */
|
||||
#define APIC_OFFSET_TPR 0x80 /* Task Priority Register */
|
||||
#define APIC_OFFSET_APR 0x90 /* Arbitration Priority */
|
||||
#define APIC_OFFSET_PPR 0xA0 /* Processor Priority Register */
|
||||
#define APIC_OFFSET_EOI 0xB0 /* EOI Register */
|
||||
#define APIC_OFFSET_RRR 0xC0 /* Remote read */
|
||||
#define APIC_OFFSET_LDR 0xD0 /* Logical Destination */
|
||||
#define APIC_OFFSET_DFR 0xE0 /* Destination Format Register */
|
||||
#define APIC_OFFSET_SVR 0xF0 /* Spurious Vector Register */
|
||||
#define APIC_OFFSET_ISR0 0x100 /* In Service Register */
|
||||
#define APIC_OFFSET_ISR1 0x110
|
||||
#define APIC_OFFSET_ISR2 0x120
|
||||
#define APIC_OFFSET_ISR3 0x130
|
||||
#define APIC_OFFSET_ISR4 0x140
|
||||
#define APIC_OFFSET_ISR5 0x150
|
||||
#define APIC_OFFSET_ISR6 0x160
|
||||
#define APIC_OFFSET_ISR7 0x170
|
||||
#define APIC_OFFSET_TMR0 0x180 /* Trigger Mode Register */
|
||||
#define APIC_OFFSET_TMR1 0x190
|
||||
#define APIC_OFFSET_TMR2 0x1A0
|
||||
#define APIC_OFFSET_TMR3 0x1B0
|
||||
#define APIC_OFFSET_TMR4 0x1C0
|
||||
#define APIC_OFFSET_TMR5 0x1D0
|
||||
#define APIC_OFFSET_TMR6 0x1E0
|
||||
#define APIC_OFFSET_TMR7 0x1F0
|
||||
#define APIC_OFFSET_IRR0 0x200 /* Interrupt Request Register */
|
||||
#define APIC_OFFSET_IRR1 0x210
|
||||
#define APIC_OFFSET_IRR2 0x220
|
||||
#define APIC_OFFSET_IRR3 0x230
|
||||
#define APIC_OFFSET_IRR4 0x240
|
||||
#define APIC_OFFSET_IRR5 0x250
|
||||
#define APIC_OFFSET_IRR6 0x260
|
||||
#define APIC_OFFSET_IRR7 0x270
|
||||
#define APIC_OFFSET_ESR 0x280 /* Error Status Register */
|
||||
#define APIC_OFFSET_CMCI_LVT 0x2F0 /* Local Vector Table (CMCI) */
|
||||
#define APIC_OFFSET_ICR_LOW 0x300 /* Interrupt Command Register */
|
||||
#define APIC_OFFSET_ICR_HI 0x310
|
||||
#define APIC_OFFSET_TIMER_LVT 0x320 /* Local Vector Table (Timer) */
|
||||
#define APIC_OFFSET_THERM_LVT 0x330 /* Local Vector Table (Thermal) */
|
||||
#define APIC_OFFSET_PERF_LVT 0x340 /* Local Vector Table (PMC) */
|
||||
#define APIC_OFFSET_LINT0_LVT 0x350 /* Local Vector Table (LINT0) */
|
||||
#define APIC_OFFSET_LINT1_LVT 0x360 /* Local Vector Table (LINT1) */
|
||||
#define APIC_OFFSET_ERROR_LVT 0x370 /* Local Vector Table (ERROR) */
|
||||
#define APIC_OFFSET_TIMER_ICR 0x380 /* Timer's Initial Count */
|
||||
#define APIC_OFFSET_TIMER_CCR 0x390 /* Timer's Current Count */
|
||||
#define APIC_OFFSET_TIMER_DCR 0x3E0 /* Timer's Divide Configuration */
|
||||
#define APIC_OFFSET_SELF_IPI 0x3F0 /* Self IPI register */
|
||||
#define APIC_OFFSET_ID 0x20U /* Local APIC ID */
|
||||
#define APIC_OFFSET_VER 0x30U /* Local APIC Version */
|
||||
#define APIC_OFFSET_TPR 0x80U /* Task Priority Register */
|
||||
#define APIC_OFFSET_APR 0x90U /* Arbitration Priority */
|
||||
#define APIC_OFFSET_PPR 0xA0U /* Processor Priority Register */
|
||||
#define APIC_OFFSET_EOI 0xB0U /* EOI Register */
|
||||
#define APIC_OFFSET_RRR 0xC0U /* Remote read */
|
||||
#define APIC_OFFSET_LDR 0xD0U /* Logical Destination */
|
||||
#define APIC_OFFSET_DFR 0xE0U /* Destination Format Register */
|
||||
#define APIC_OFFSET_SVR 0xF0U /* Spurious Vector Register */
|
||||
#define APIC_OFFSET_ISR0 0x100U /* In Service Register */
|
||||
#define APIC_OFFSET_ISR1 0x110U
|
||||
#define APIC_OFFSET_ISR2 0x120U
|
||||
#define APIC_OFFSET_ISR3 0x130U
|
||||
#define APIC_OFFSET_ISR4 0x140U
|
||||
#define APIC_OFFSET_ISR5 0x150U
|
||||
#define APIC_OFFSET_ISR6 0x160U
|
||||
#define APIC_OFFSET_ISR7 0x170U
|
||||
#define APIC_OFFSET_TMR0 0x180U /* Trigger Mode Register */
|
||||
#define APIC_OFFSET_TMR1 0x190U
|
||||
#define APIC_OFFSET_TMR2 0x1A0U
|
||||
#define APIC_OFFSET_TMR3 0x1B0U
|
||||
#define APIC_OFFSET_TMR4 0x1C0U
|
||||
#define APIC_OFFSET_TMR5 0x1D0U
|
||||
#define APIC_OFFSET_TMR6 0x1E0U
|
||||
#define APIC_OFFSET_TMR7 0x1F0U
|
||||
#define APIC_OFFSET_IRR0 0x200U /* Interrupt Request Register */
|
||||
#define APIC_OFFSET_IRR1 0x210U
|
||||
#define APIC_OFFSET_IRR2 0x220U
|
||||
#define APIC_OFFSET_IRR3 0x230U
|
||||
#define APIC_OFFSET_IRR4 0x240U
|
||||
#define APIC_OFFSET_IRR5 0x250U
|
||||
#define APIC_OFFSET_IRR6 0x260U
|
||||
#define APIC_OFFSET_IRR7 0x270U
|
||||
#define APIC_OFFSET_ESR 0x280U /* Error Status Register */
|
||||
#define APIC_OFFSET_CMCI_LVT 0x2F0U /* Local Vector Table (CMCI) */
|
||||
#define APIC_OFFSET_ICR_LOW 0x300U /* Interrupt Command Register */
|
||||
#define APIC_OFFSET_ICR_HI 0x310U
|
||||
#define APIC_OFFSET_TIMER_LVT 0x320U /* Local Vector Table (Timer) */
|
||||
#define APIC_OFFSET_THERM_LVT 0x330U /* Local Vector Table (Thermal) */
|
||||
#define APIC_OFFSET_PERF_LVT 0x340U /* Local Vector Table (PMC) */
|
||||
#define APIC_OFFSET_LINT0_LVT 0x350U /* Local Vector Table (LINT0) */
|
||||
#define APIC_OFFSET_LINT1_LVT 0x360U /* Local Vector Table (LINT1) */
|
||||
#define APIC_OFFSET_ERROR_LVT 0x370U /* Local Vector Table (ERROR) */
|
||||
#define APIC_OFFSET_TIMER_ICR 0x380U /* Timer's Initial Count */
|
||||
#define APIC_OFFSET_TIMER_CCR 0x390U /* Timer's Current Count */
|
||||
#define APIC_OFFSET_TIMER_DCR 0x3E0U /* Timer's Divide Configuration */
|
||||
#define APIC_OFFSET_SELF_IPI 0x3F0U /* Self IPI register */
|
||||
|
||||
/*
|
||||
* 16 priority levels with at most one vector injected per level.
|
||||
|
||||
@ -272,7 +272,7 @@ struct ioapic {
|
||||
|
||||
/* constants relating to APIC ID registers */
|
||||
#define APIC_ID_MASK 0xff000000U
|
||||
#define APIC_ID_SHIFT 24
|
||||
#define APIC_ID_SHIFT 24U
|
||||
#define APIC_ID_CLUSTER 0xf0U
|
||||
#define APIC_ID_CLUSTER_ID 0x0fU
|
||||
#define APIC_MAX_CLUSTER 0xeU
|
||||
@ -282,7 +282,7 @@ struct ioapic {
|
||||
/* fields in VER */
|
||||
#define APIC_VER_VERSION 0x000000ffU
|
||||
#define APIC_VER_MAXLVT 0x00ff0000U
|
||||
#define MAXLVTSHIFT 16
|
||||
#define MAXLVTSHIFT 16U
|
||||
#define APIC_VER_EOI_SUPPRESSION 0x01000000U
|
||||
#define APIC_VER_AMD_EXT_SPACE 0x80000000U
|
||||
|
||||
|
||||
@ -58,7 +58,7 @@
|
||||
#define VMX_EOI_EXIT2_HIGH 0x00002021U
|
||||
#define VMX_EOI_EXIT3_FULL 0x00002022U
|
||||
#define VMX_EOI_EXIT3_HIGH 0x00002023U
|
||||
#define VMX_EOI_EXIT(vector) (VMX_EOI_EXIT0_FULL + ((vector) / 64) * 2)
|
||||
#define VMX_EOI_EXIT(vector) (VMX_EOI_EXIT0_FULL + ((vector) / 64U) * 2U)
|
||||
#define VMX_XSS_EXITING_BITMAP_FULL 0x0000202CU
|
||||
#define VMX_XSS_EXITING_BITMAP_HIGH 0x0000202DU
|
||||
/* 64-bit read-only data fields */
|
||||
@ -376,7 +376,7 @@
|
||||
* 15 = guest-physical access for an instructon fetch or during
|
||||
* instruction execution
|
||||
*/
|
||||
#define APIC_ACCESS_TYPE(qual) (((qual) >> 12) & 0xFU)
|
||||
#define APIC_ACCESS_TYPE(qual) (((qual) >> 12U) & 0xFUL)
|
||||
#define APIC_ACCESS_OFFSET(qual) ((qual) & 0xFFFU)
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user