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HV: io: unify vhm_request req and mem_io in vcpu

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The current struct vcpu has two members, namely 'struct vhm_request req' and
'struct mem_io mmio', that hold similar info, including the address, direction, size,
value and status of mmio reqeusts.

As a step towards a unified framework for both MMIO/PIO, this patch unifies
these two members by a tailored version of vhm_reqeust, mostly with the reserved
fields dropped. The definitions to request types, directions and process status
are reused.

Handling errors during emulations will be revisited after the I/O emulation
paths are unified. Thus for this patch the mmio.mmio_status in inherited by
io_req.processed which is not yet properly processed.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Junjie Mao
2018-07-24 19:05:47 +08:00
committed by lijinxia
parent 1915eec632
commit 88f74b5dbb
12 changed files with 180 additions and 181 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
hypervisor/arch/x86/guest/instr_emul_wrapper.c
View File

@@ -243,7 +243,7 @@ encode_vmcs_seg_desc(enum cpu_reg_name seg,
*
*Post Condition:
*In the non-general register names group (CPU_REG_CR0~CPU_REG_GDTR),
*for register names CPU_REG_CR2, CPU_REG_IDTR and CPU_REG_GDTR,
*for register names CPU_REG_CR2, CPU_REG_IDTR and CPU_REG_GDTR,
*this function returns VMX_INVALID_VMCS_FIELD;
*for other register names, it returns correspoding field index MACROs
*in VMCS.
@@ -319,7 +319,7 @@ static int mmio_read(struct vcpu *vcpu, __unused uint64_t gpa, uint64_t *rval,
return -EINVAL;
}
*rval = vcpu->mmio.value;
*rval = vcpu->req.reqs.mmio.value;
return 0;
}
@@ -330,7 +330,7 @@ static int mmio_write(struct vcpu *vcpu, __unused uint64_t gpa, uint64_t wval,
return -EINVAL;
}
vcpu->mmio.value = wval;
vcpu->req.reqs.mmio.value = wval;
return 0;
}
@@ -375,7 +375,7 @@ int emulate_instruction(struct vcpu *vcpu)
struct emul_ctxt *emul_ctxt;
struct vm_guest_paging *paging;
int retval = 0;
uint64_t gpa = vcpu->mmio.paddr;
uint64_t gpa = vcpu->req.reqs.mmio.address;
mem_region_read_t mread = mmio_read;
mem_region_write_t mwrite = mmio_write;

2
hypervisor/arch/x86/guest/vcpu.c
View File

@@ -122,6 +122,8 @@ int create_vcpu(uint16_t pcpu_id, struct vm *vm, struct vcpu **rtn_vcpu_handle)
vcpu->pending_pre_work = 0U;
vcpu->state = VCPU_INIT;
(void)memset(&vcpu->req, 0U, sizeof(struct io_request));
return 0;
}

21
hypervisor/arch/x86/guest/vioapic.c
View File

@@ -596,32 +596,31 @@ vioapic_pincount(struct vm *vm)
}
}
int vioapic_mmio_access_handler(struct vcpu *vcpu, struct mem_io *mmio,
int vioapic_mmio_access_handler(struct vcpu *vcpu, struct io_request *io_req,
__unused void *handler_private_data)
{
struct vm *vm = vcpu->vm;
uint64_t gpa = mmio->paddr;
struct mmio_request *mmio = &io_req->reqs.mmio;
uint64_t gpa = mmio->address;
int ret = 0;
/* Note all RW to IOAPIC are 32-Bit in size */
if (mmio->access_size == 4U) {
uint32_t data = mmio->value;
if (mmio->size == 4UL) {
uint32_t data = (uint32_t)mmio->value;
if (mmio->read_write == HV_MEM_IO_READ) {
if (mmio->direction == REQUEST_READ) {
vioapic_mmio_read(vm,
gpa,
&data);
mmio->value = (uint64_t)data;
mmio->mmio_status = MMIO_TRANS_VALID;
} else if (mmio->read_write == HV_MEM_IO_WRITE) {
io_req->processed = REQ_STATE_SUCCESS;
} else if (mmio->direction == REQUEST_WRITE) {
vioapic_mmio_write(vm,
gpa,
data);
mmio->mmio_status = MMIO_TRANS_VALID;
io_req->processed = REQ_STATE_SUCCESS;
} else {
/* Can never happen due to the range of read_write. */
/* Can never happen due to the range of direction. */
}
} else {
pr_err("All RW to IOAPIC must be 32-bits in size");

35
hypervisor/arch/x86/guest/vlapic.c
View File

@@ -2054,32 +2054,30 @@ vlapic_read_mmio_reg(struct vcpu *vcpu, uint64_t gpa, uint64_t *rval,
return error;
}
int vlapic_mmio_access_handler(struct vcpu *vcpu, struct mem_io *mmio,
int vlapic_mmio_access_handler(struct vcpu *vcpu, struct io_request *io_req,
__unused void *handler_private_data)
{
uint64_t gpa = mmio->paddr;
struct mmio_request *mmio_req = &io_req->reqs.mmio;
uint64_t gpa = mmio_req->address;
int ret = 0;
/* Note all RW to LAPIC are 32-Bit in size */
ASSERT(mmio->access_size == 4U,
"All RW to LAPIC must be 32-bits in size");
ASSERT(mmio_req->size == 4UL, "All RW to LAPIC must be 32-bits in size");
if (mmio->read_write == HV_MEM_IO_READ) {
if (mmio_req->direction == REQUEST_READ) {
ret = vlapic_read_mmio_reg(vcpu,
gpa,
&mmio->value,
mmio->access_size);
mmio->mmio_status = MMIO_TRANS_VALID;
} else if (mmio->read_write == HV_MEM_IO_WRITE) {
&mmio_req->value,
mmio_req->size);
io_req->processed = REQ_STATE_SUCCESS;
} else if (mmio_req->direction == REQUEST_WRITE) {
ret = vlapic_write_mmio_reg(vcpu,
gpa,
mmio->value,
mmio->access_size);
mmio->mmio_status = MMIO_TRANS_VALID;
mmio_req->value,
mmio_req->size);
io_req->processed = REQ_STATE_SUCCESS;
} else {
/* Can never happen due to the range of mmio->read_write. */
/* Can never happen due to the range of mmio_req->direction. */
}
return ret;
@@ -2354,7 +2352,7 @@ apicv_inject_pir(struct vlapic *vlapic)
if (pirval != 0UL) {
rvi = pirbase + fls64(pirval);
intr_status_old = 0xFFFFU &
intr_status_old = 0xFFFFU &
exec_vmread16(VMX_GUEST_INTR_STATUS);
intr_status_new = (intr_status_old & 0xFF00U) | rvi;
@@ -2371,6 +2369,7 @@ int apic_access_vmexit_handler(struct vcpu *vcpu)
uint32_t offset = 0U;
uint64_t qual, access_type;
struct vlapic *vlapic;
struct mmio_request *mmio = &vcpu->req.reqs.mmio;
qual = vcpu->arch_vcpu.exit_qualification;
access_type = APIC_ACCESS_TYPE(qual);
@@ -2392,10 +2391,10 @@ int apic_access_vmexit_handler(struct vcpu *vcpu)
if (access_type == 1UL) {
if (emulate_instruction(vcpu) == 0) {
err = vlapic_write(vlapic, 1, offset, vcpu->mmio.value);
err = vlapic_write(vlapic, 1, offset, mmio->value);
}
} else if (access_type == 0UL) {
err = vlapic_read(vlapic, 1, offset, &vcpu->mmio.value);
err = vlapic_read(vlapic, 1, offset, &mmio->value);
if (err < 0) {
return err;
}