From 89c25b008a7190d2ec6f426d865b7fb6c9813fc9 Mon Sep 17 00:00:00 2001 From: Fei Li Date: Fri, 23 Jul 2021 08:59:35 +0800 Subject: [PATCH] hv: vpci: modify Interrupt Line Register as writable According to PCIe Spec, for a RW register bits, If the optional feature that is associated with the bits is not implemented, the bits are permitted to be hardwired to 0b. However Zephyr would use INTx Line Register as writable even this PCI device has no INTx, so emulate INTx Line Register as writable. Tracked-On: #6330 Signed-off-by: Fei Li --- hypervisor/dm/vpci/vpci.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hypervisor/dm/vpci/vpci.c b/hypervisor/dm/vpci/vpci.c index eb632d5e4..e9e90d14b 100644 --- a/hypervisor/dm/vpci/vpci.c +++ b/hypervisor/dm/vpci/vpci.c @@ -482,6 +482,17 @@ static void write_cfg_header(struct pci_vdev *vdev, pci_vdev_write_vcfg(vdev, offset, bytes, val); } } + + /* According to PCIe Spec, for a RW register bits, If the optional feature + * that is associated with the bits is not implemented, the bits are permitted + * to be hardwired to 0b. However Zephyr would use INTx Line Register as writable + * even this PCI device has no INTx, so emulate INTx Line Register as writable. + */ + if (offset == PCIR_INTERRUPT_LINE) { + val &= 0xfU; + pci_vdev_write_vcfg(vdev, offset, bytes, val); + } + } }