diff --git a/hypervisor/arch/x86/guest/vcpuid.c b/hypervisor/arch/x86/guest/vcpuid.c
index 1b688d13b..e2d5d4e0a 100644
--- a/hypervisor/arch/x86/guest/vcpuid.c
+++ b/hypervisor/arch/x86/guest/vcpuid.c
@@ -119,6 +119,7 @@ static void init_vcpuid_entry(uint32_t leaf, uint32_t subleaf,
 		cpuid_subleaf(leaf, subleaf, &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
 		/* Always hide package level HWP controls and HWP interrupt*/
 		entry->eax &= ~(CPUID_EAX_HWP_CTL | CPUID_EAX_HWP_PLR | CPUID_EAX_HWP_N);
+		entry->eax &= ~(CPUID_EAX_HFI | CPUID_EAX_ITD);
 		break;
 
 	case 0x07U:
diff --git a/hypervisor/arch/x86/guest/vmsr.c b/hypervisor/arch/x86/guest/vmsr.c
index ede0ccdad..25dc74f13 100644
--- a/hypervisor/arch/x86/guest/vmsr.c
+++ b/hypervisor/arch/x86/guest/vmsr.c
@@ -280,6 +280,16 @@ static const uint32_t unsupported_msrs[] = {
 	 * CPUID.06H.EAX[8]
 	 */
 	MSR_IA32_HWP_INTERRUPT,
+
+	/*
+	 * HFI and IDT registers disabled:
+	 * CPUID.06H.EAX[19]
+	 * CPUID.06H.EAX[23]
+	 */
+	IA32_HW_FEEDBACK_PTR,
+	IA32_HW_FEEDBACK_CONFIG,
+	IA32_THREAD_FEEDBACK_CHAR,
+	IA32_HW_FEEDBACK_THREAD_CONFIG,
 };
 
 /* emulated_guest_msrs[] shares same indexes with array vcpu->arch->guest_msrs[] */
diff --git a/hypervisor/include/arch/x86/asm/cpuid.h b/hypervisor/include/arch/x86/asm/cpuid.h
index 022ac5850..70a4d0748 100644
--- a/hypervisor/include/arch/x86/asm/cpuid.h
+++ b/hypervisor/include/arch/x86/asm/cpuid.h
@@ -84,8 +84,12 @@
 #define CPUID_EAX_HWP_EPP       (1U<<10U)
 /* CPUID.06H:EAX.HWP_Package_Level_Request */
 #define CPUID_EAX_HWP_PLR       (1U<<11U)
+/* CPUID.06H:EAX.Hardware_Feedback_Interface */
+#define CPUID_EAX_HFI           (1U<<19U)
 /* CPUID.06H:EAX.HWP_control */
 #define CPUID_EAX_HWP_CTL       (1U<<22U)
+/* CPUID.06H:EAX.Intel_Thread_Director */
+#define CPUID_EAX_ITD           (1U<<23U)
 /* CPUID.06H:ECX.Hardware_Coordination_Feedback_Capability */
 #define CPUID_ECX_HCFC          (1U<<0U)
 /* CPUID.07H:EBX.FSGSBASE*/
diff --git a/hypervisor/include/arch/x86/asm/msr.h b/hypervisor/include/arch/x86/asm/msr.h
index b2e56ec5f..42d4708c8 100644
--- a/hypervisor/include/arch/x86/asm/msr.h
+++ b/hypervisor/include/arch/x86/asm/msr.h
@@ -533,6 +533,11 @@
 #define MSR_EMON_L3_CTR_CTL6			0x000107D2U
 #define MSR_EMON_L3_CTR_CTL7			0x000107D3U
 
+#define IA32_HW_FEEDBACK_PTR			0x17d0U
+#define IA32_HW_FEEDBACK_CONFIG			0x17d1U
+#define IA32_THREAD_FEEDBACK_CHAR		0x17d2U
+#define IA32_HW_FEEDBACK_THREAD_CONFIG		0x17d4U
+
 #ifdef PROFILING_ON
 /* Core (and Goldmont) specific MSRs */
 #define MSR_CORE_LASTBRANCH_TOS			0x000001C9U