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https://github.com/projectacrn/acrn-hypervisor.git
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hv: pass pointer to functions
Pass intr_src and dmar_ir_entry irte as pointers to dmar_assign_irte(), which fixes the "Attempt to change parameter passed by value" MISRA C violation. A few coding style fixes Tracked-On: #4506 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
dongshen
wenlingz
parent
cc5bc34acb
commit
8be6c87841
@ -77,7 +77,7 @@ static void ptirq_free_irte(const struct ptirq_remapping_info *entry)
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intr_src.src.ioapic_id = ioapic_irq_to_ioapic_id(entry->allocated_pirq);
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}
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dmar_free_irte(intr_src, (uint16_t)entry->allocated_pirq);
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dmar_free_irte(&intr_src, (uint16_t)entry->allocated_pirq);
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}
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static void ptirq_build_physical_msi(struct acrn_vm *vm, struct ptirq_msi_info *info,
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@ -117,7 +117,7 @@ static void ptirq_build_physical_msi(struct acrn_vm *vm, struct ptirq_msi_info *
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intr_src.is_msi = true;
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intr_src.src.msi.value = entry->phys_sid.msi_id.bdf;
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ret = dmar_assign_irte(intr_src, irte, (uint16_t)entry->allocated_pirq);
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ret = dmar_assign_irte(&intr_src, &irte, (uint16_t)entry->allocated_pirq);
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if (ret == 0) {
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/*
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@ -213,7 +213,7 @@ ptirq_build_physical_rte(struct acrn_vm *vm, struct ptirq_remapping_info *entry)
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intr_src.is_msi = false;
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intr_src.src.ioapic_id = ioapic_irq_to_ioapic_id(phys_irq);
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ret = dmar_assign_irte(intr_src, irte, (uint16_t)phys_irq);
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ret = dmar_assign_irte(&intr_src, &irte, (uint16_t)phys_irq);
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if (ret == 0) {
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ir_index.index = (uint16_t)phys_irq;
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@ -299,7 +299,8 @@ static struct ptirq_remapping_info *add_msix_remapping(struct acrn_vm *vm,
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}
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} else {
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/* The mapping has already been added to the VM. No action
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* required. */
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* required.
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*/
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}
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dev_dbg(DBG_LEVEL_IRQ, "VM%d MSIX add vector mapping vbdf%x:pbdf%x idx=%d",
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@ -325,7 +326,7 @@ remove_msix_remapping(const struct acrn_vm *vm, uint16_t virt_bdf, uint32_t entr
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intr_src.is_msi = true;
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intr_src.src.msi.value = entry->phys_sid.msi_id.bdf;
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dmar_free_irte(intr_src, (uint16_t)entry->allocated_pirq);
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dmar_free_irte(&intr_src, (uint16_t)entry->allocated_pirq);
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dev_dbg(DBG_LEVEL_IRQ,
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"VM%d MSIX remove vector mapping vbdf-pbdf:0x%x-0x%x idx=%d",
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@ -380,7 +381,8 @@ static struct ptirq_remapping_info *add_intx_remapping(struct acrn_vm *vm, uint3
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}
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} else {
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/* The mapping has already been added to the VM. No action
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* required. */
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* required.
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*/
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}
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@ -415,7 +417,7 @@ static void remove_intx_remapping(const struct acrn_vm *vm, uint32_t virt_gsi, e
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intr_src.is_msi = false;
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intr_src.src.ioapic_id = ioapic_irq_to_ioapic_id(phys_irq);
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dmar_free_irte(intr_src, (uint16_t)phys_irq);
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dmar_free_irte(&intr_src, (uint16_t)phys_irq);
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dev_dbg(DBG_LEVEL_IRQ,
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"deactive %s intx entry:pgsi=%d, pirq=%d ",
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(vgsi_ctlr == INTX_CTLR_PIC) ? "vPIC" : "vIOAPIC",
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@ -432,6 +434,7 @@ static void ptirq_handle_intx(struct acrn_vm *vm,
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const struct ptirq_remapping_info *entry)
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{
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const union source_id *virt_sid = &entry->virt_sid;
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switch (virt_sid->intx_id.ctlr) {
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case INTX_CTLR_IOAPIC:
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{
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@ -597,6 +600,7 @@ int32_t ptirq_prepare_msix_remap(struct acrn_vm *vm, uint16_t virt_bdf, uint16_t
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/* build physical config MSI, update to info->pmsi_xxx */
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if (is_lapic_pt_configured(vm)) {
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enum vm_vlapic_state vlapic_state = check_vm_vlapic_state(vm);
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if (vlapic_state == VM_VLAPIC_X2APIC) {
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/*
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* All the vCPUs are in x2APIC mode and LAPIC is Pass-through
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@ -1387,7 +1387,7 @@ int32_t init_iommu(void)
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return ret;
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}
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int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte, uint16_t index)
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int32_t dmar_assign_irte(const struct intr_source *intr_src, union dmar_ir_entry *irte, uint16_t index)
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{
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struct dmar_drhd_rt *dmar_unit;
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union dmar_ir_entry *ir_table, *ir_entry;
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@ -1395,13 +1395,13 @@ int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte,
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uint64_t trigger_mode;
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int32_t ret = 0;
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if (intr_src.is_msi) {
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dmar_unit = device_to_dmaru((uint8_t)intr_src.src.msi.bits.b, intr_src.src.msi.fields.devfun);
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sid.value = intr_src.src.msi.value;
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if (intr_src->is_msi) {
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dmar_unit = device_to_dmaru((uint8_t)intr_src->src.msi.bits.b, intr_src->src.msi.fields.devfun);
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sid.value = (uint16_t)(intr_src->src.msi.value);
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trigger_mode = 0x0UL;
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} else {
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dmar_unit = ioapic_to_dmaru(intr_src.src.ioapic_id, &sid);
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trigger_mode = irte.bits.trigger_mode;
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dmar_unit = ioapic_to_dmaru(intr_src->src.ioapic_id, &sid);
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trigger_mode = irte->bits.trigger_mode;
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}
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if (dmar_unit == NULL) {
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@ -1415,17 +1415,17 @@ int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte,
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ret = -EINVAL;
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} else {
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dmar_enable_intr_remapping(dmar_unit);
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irte.bits.svt = 0x1UL;
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irte.bits.sq = 0x0UL;
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irte.bits.sid = sid.value;
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irte.bits.present = 0x1UL;
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irte.bits.mode = 0x0UL;
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irte.bits.trigger_mode = trigger_mode;
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irte.bits.fpd = 0x0UL;
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irte->bits.svt = 0x1UL;
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irte->bits.sq = 0x0UL;
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irte->bits.sid = sid.value;
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irte->bits.present = 0x1UL;
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irte->bits.mode = 0x0UL;
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irte->bits.trigger_mode = trigger_mode;
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irte->bits.fpd = 0x0UL;
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ir_table = (union dmar_ir_entry *)hpa2hva(dmar_unit->ir_table_addr);
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ir_entry = ir_table + index;
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ir_entry->entry.hi_64 = irte.entry.hi_64;
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ir_entry->entry.lo_64 = irte.entry.lo_64;
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ir_entry->entry.hi_64 = irte->entry.hi_64;
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ir_entry->entry.lo_64 = irte->entry.lo_64;
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iommu_flush_cache(ir_entry, sizeof(union dmar_ir_entry));
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dmar_invalid_iec(dmar_unit, index, 0U, false);
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@ -1433,24 +1433,24 @@ int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte,
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return ret;
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}
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void dmar_free_irte(struct intr_source intr_src, uint16_t index)
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void dmar_free_irte(const struct intr_source *intr_src, uint16_t index)
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{
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struct dmar_drhd_rt *dmar_unit;
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union dmar_ir_entry *ir_table, *ir_entry;
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union pci_bdf sid;
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if (intr_src.is_msi) {
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dmar_unit = device_to_dmaru((uint8_t)intr_src.src.msi.bits.b, intr_src.src.msi.fields.devfun);
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if (intr_src->is_msi) {
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dmar_unit = device_to_dmaru((uint8_t)intr_src->src.msi.bits.b, intr_src->src.msi.fields.devfun);
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} else {
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dmar_unit = ioapic_to_dmaru(intr_src.src.ioapic_id, &sid);
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dmar_unit = ioapic_to_dmaru(intr_src->src.ioapic_id, &sid);
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}
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if (dmar_unit == NULL) {
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pr_err("no dmar unit found for device: %x:%x.%x", intr_src.src.msi.bits.b,
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intr_src.src.msi.bits.d, intr_src.src.msi.bits.f);
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pr_err("no dmar unit found for device: %x:%x.%x", intr_src->src.msi.bits.b,
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intr_src->src.msi.bits.d, intr_src->src.msi.bits.f);
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} else if (dmar_unit->drhd->ignore) {
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dev_dbg(DBG_LEVEL_IOMMU, "device is ignored :0x%x:%x.%x", intr_src.src.msi.bits.b,
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intr_src.src.msi.bits.d, intr_src.src.msi.bits.f);
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dev_dbg(DBG_LEVEL_IOMMU, "device is ignored :0x%x:%x.%x", intr_src->src.msi.bits.b,
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intr_src->src.msi.bits.d, intr_src->src.msi.bits.f);
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} else if (dmar_unit->ir_table_addr == 0UL) {
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pr_err("IR table is not set for dmar unit");
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} else {
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@ -668,7 +668,7 @@ bool iommu_snoop_supported(const struct iommu_domain *iommu);
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* @retval 0 otherwise
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*
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*/
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int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte, uint16_t index);
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int32_t dmar_assign_irte(const struct intr_source *intr_src, union dmar_ir_entry *irte, uint16_t index);
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/**
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* @brief Free RTE for Interrupt Remapping Table.
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@ -677,7 +677,7 @@ int32_t dmar_assign_irte(struct intr_source intr_src, union dmar_ir_entry irte,
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* @param[in] index into Interrupt Remapping Table
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*
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*/
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void dmar_free_irte(struct intr_source intr_src, uint16_t index);
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void dmar_free_irte(const struct intr_source *intr_src, uint16_t index);
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/**
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* @brief Flash cacheline(s) for a specific address with specific size.
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