mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2026-06-09 02:24:45 +00:00
dm: Reorganize ACRN DM directory.
The current dm, all non-pci and non-acpi related files are put into hw/platform directory. This is actually disturbed the meaning of *platform*. The platform devices are mean of board and SoC specific non-PCI devices, like usb devices, etc. This patch refines the ACRN dm directory architecture. For some common device logic files, likes block_if.c/uart_core.c or usb_core.c. They will move to hw/ directly. For platform architecture depended files, create arch/ under root dir. And create sub-dir arch/x86 for x86 architecture, will create more architectures in future. The pm.c will move to this new dir. The hw/acpi will be moved to hw/platform/acpi due to acpi also be considered as part of platform. Signed-off-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Yu Wang
Jack Ren
1031
devicemodel/hw/platform/acpi/acpi.c
Normal file
1031
devicemodel/hw/platform/acpi/acpi.c
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File diff suppressed because it is too large
Load Diff
387
devicemodel/hw/platform/acpi/acpi_pm.c
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387
devicemodel/hw/platform/acpi/acpi_pm.c
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@@ -0,0 +1,387 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <stdbool.h>
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#include "vmm.h"
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#include "vmmapi.h"
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#include "dm.h"
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#include "acpi.h"
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static inline int get_vcpu_pm_info(struct vmctx *ctx, int vcpu_id,
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uint64_t pm_type, uint64_t *pm_info)
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{
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*pm_info = ((ctx->vmid << PMCMD_VMID_SHIFT) & PMCMD_VMID_MASK)
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| ((vcpu_id << PMCMD_VCPUID_SHIFT) & PMCMD_VCPUID_MASK)
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| (pm_type & PMCMD_TYPE_MASK);
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return vm_get_cpu_state(ctx, pm_info);
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}
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static inline uint8_t get_vcpu_px_cnt(struct vmctx *ctx, int vcpu_id)
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{
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uint64_t px_cnt;
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if (get_vcpu_pm_info(ctx, vcpu_id, PMCMD_GET_PX_CNT, &px_cnt)) {
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return 0;
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}
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return (uint8_t)px_cnt;
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}
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uint8_t get_vcpu_cx_cnt(struct vmctx *ctx, int vcpu_id)
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{
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uint64_t cx_cnt;
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if (get_vcpu_pm_info(ctx, vcpu_id, PMCMD_GET_CX_CNT, &cx_cnt)) {
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return 0;
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}
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return (uint8_t)cx_cnt;
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}
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static int get_vcpu_px_data(struct vmctx *ctx, int vcpu_id,
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int px_num, struct cpu_px_data *vcpu_px_data)
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{
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uint64_t *pm_ioctl_buf;
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enum pm_cmd_type cmd_type = PMCMD_GET_PX_DATA;
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pm_ioctl_buf = malloc(sizeof(struct cpu_px_data));
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if (!pm_ioctl_buf) {
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return -1;
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}
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*pm_ioctl_buf = ((ctx->vmid << PMCMD_VMID_SHIFT) & PMCMD_VMID_MASK)
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| ((vcpu_id << PMCMD_VCPUID_SHIFT) & PMCMD_VCPUID_MASK)
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| ((px_num << PMCMD_STATE_NUM_SHIFT) & PMCMD_STATE_NUM_MASK)
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| cmd_type;
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/* get and validate px data */
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if (vm_get_cpu_state(ctx, pm_ioctl_buf)) {
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free(pm_ioctl_buf);
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return -1;
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}
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memcpy(vcpu_px_data, pm_ioctl_buf,
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sizeof(struct cpu_px_data));
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free(pm_ioctl_buf);
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return 0;
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}
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int get_vcpu_cx_data(struct vmctx *ctx, int vcpu_id,
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int cx_num, struct cpu_cx_data *vcpu_cx_data)
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{
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uint64_t *pm_ioctl_buf;
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enum pm_cmd_type cmd_type = PMCMD_GET_CX_DATA;
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pm_ioctl_buf = malloc(sizeof(struct cpu_cx_data));
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if (!pm_ioctl_buf) {
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return -1;
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}
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*pm_ioctl_buf = ((ctx->vmid << PMCMD_VMID_SHIFT) & PMCMD_VMID_MASK)
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| ((vcpu_id << PMCMD_VCPUID_SHIFT) & PMCMD_VCPUID_MASK)
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| ((cx_num << PMCMD_STATE_NUM_SHIFT) & PMCMD_STATE_NUM_MASK)
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| cmd_type;
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/* get and validate cx data */
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if (vm_get_cpu_state(ctx, pm_ioctl_buf)) {
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free(pm_ioctl_buf);
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return -1;
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}
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memcpy(vcpu_cx_data, pm_ioctl_buf,
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sizeof(struct cpu_cx_data));
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free(pm_ioctl_buf);
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return 0;
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}
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char *_asi_table[7] = { "SystemMemory",
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"SystemIO",
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"PCI_Config",
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"EmbeddedControl",
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"SMBus",
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"PCC",
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"FFixedHW"};
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static char *get_asi_string(uint8_t space_id)
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{
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switch (space_id) {
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case SPACE_SYSTEM_MEMORY:
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return _asi_table[0];
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case SPACE_SYSTEM_IO:
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return _asi_table[1];
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case SPACE_PCI_CONFIG:
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return _asi_table[2];
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case SPACE_Embedded_Control:
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return _asi_table[3];
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case SPACE_SMBUS:
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return _asi_table[4];
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case SPACE_PLATFORM_COMM:
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return _asi_table[5];
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case SPACE_FFixedHW:
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return _asi_table[6];
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default:
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return NULL;
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}
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}
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/* _CST: C-States
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*/
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void dsdt_write_cst(struct vmctx *ctx, int vcpu_id)
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{
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int i;
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uint8_t vcpu_cx_cnt;
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char *cx_asi;
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struct acpi_generic_address cx_reg;
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struct cpu_cx_data *vcpu_cx_data;
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vcpu_cx_cnt = get_vcpu_cx_cnt(ctx, vcpu_id);
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if (!vcpu_cx_cnt) {
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return;
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}
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/* vcpu_cx_data start from C1, cx_cnt is total Cx entry num. */
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vcpu_cx_data = malloc(vcpu_cx_cnt * sizeof(struct cpu_cx_data));
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if (!vcpu_cx_data) {
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return;
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}
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/* copy and validate cx data first */
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for (i = 1; i <= vcpu_cx_cnt; i++) {
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if (get_vcpu_cx_data(ctx, vcpu_id, i, vcpu_cx_data + i - 1)) {
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/* something must be wrong, so skip the write. */
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free(vcpu_cx_data);
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return;
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}
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}
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dsdt_line("");
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dsdt_line(" Method (_CST, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (Package (0x%02X)", vcpu_cx_cnt + 1);
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dsdt_line(" {");
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dsdt_line(" 0x%02X,", vcpu_cx_cnt);
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for (i = 0; i < vcpu_cx_cnt; i++) {
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dsdt_line(" Package (0x04)");
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dsdt_line(" {");
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cx_reg = (vcpu_cx_data + i)->cx_reg;
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cx_asi = get_asi_string(cx_reg.space_id);
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dsdt_line(" ResourceTemplate ()");
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dsdt_line(" {");
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dsdt_line(" Register (%s,", cx_asi);
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dsdt_line(" 0x%02x,", cx_reg.bit_width);
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dsdt_line(" 0x%02x,", cx_reg.bit_offset);
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dsdt_line(" 0x%016lx,", cx_reg.address);
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dsdt_line(" 0x%02x,", cx_reg.access_size);
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dsdt_line(" )");
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dsdt_line(" },");
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dsdt_line(" 0x%04X,", (vcpu_cx_data + i)->type);
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dsdt_line(" 0x%04X,", (vcpu_cx_data + i)->latency);
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dsdt_line(" 0x%04X", (vcpu_cx_data + i)->power);
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if (i == (vcpu_cx_cnt - 1)) {
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dsdt_line(" }");
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} else {
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dsdt_line(" },");
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}
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}
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dsdt_line(" })");
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dsdt_line(" }");
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free(vcpu_cx_data);
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}
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/* _PPC: Performance Present Capabilities
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* hard code _PPC to 0, all states are available.
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*/
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static void dsdt_write_ppc(void)
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{
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dsdt_line(" Name (_PPC, Zero)");
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}
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/* _PCT: Performance Control
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* Both Performance Control and Status Register are set to FFixedHW
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*/
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static void dsdt_write_pct(void)
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{
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dsdt_line(" Method (_PCT, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (Package (0x02)");
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dsdt_line(" {");
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dsdt_line(" ResourceTemplate ()");
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dsdt_line(" {");
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dsdt_line(" Register (FFixedHW,");
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dsdt_line(" 0x00,");
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dsdt_line(" 0x00,");
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dsdt_line(" 0x0000000000000000,");
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dsdt_line(" ,)");
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dsdt_line(" },");
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dsdt_line("");
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dsdt_line(" ResourceTemplate ()");
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dsdt_line(" {");
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dsdt_line(" Register (FFixedHW,");
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dsdt_line(" 0x00,");
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dsdt_line(" 0x00,");
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dsdt_line(" 0x0000000000000000,");
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dsdt_line(" ,)");
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dsdt_line(" }");
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dsdt_line(" })");
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dsdt_line(" }");
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}
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/* _PSS: Performance Supported States
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*/
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static void dsdt_write_pss(struct vmctx *ctx, int vcpu_id)
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{
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uint8_t vcpu_px_cnt;
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int i;
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struct cpu_px_data *vcpu_px_data;
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vcpu_px_cnt = get_vcpu_px_cnt(ctx, vcpu_id);
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if (!vcpu_px_cnt) {
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return;
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}
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vcpu_px_data = malloc(vcpu_px_cnt * sizeof(struct cpu_px_data));
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if (!vcpu_px_data) {
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return;
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}
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/* copy and validate px data first */
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for (i = 0; i < vcpu_px_cnt; i++) {
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if (get_vcpu_px_data(ctx, vcpu_id, i, vcpu_px_data + i)) {
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/* something must be wrong, so skip the write. */
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free(vcpu_px_data);
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return;
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}
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}
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dsdt_line("");
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dsdt_line(" Method (_PSS, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (Package (0x%02X)", vcpu_px_cnt);
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dsdt_line(" {");
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for (i = 0; i < vcpu_px_cnt; i++) {
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dsdt_line(" Package (0x%02X)", 6);
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dsdt_line(" {");
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dsdt_line(" 0x%08X,",
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(vcpu_px_data + i)->core_frequency);
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dsdt_line(" 0x%08X,",
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(vcpu_px_data + i)->power);
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dsdt_line(" 0x%08X,",
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(vcpu_px_data + i)->transition_latency);
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dsdt_line(" 0x%08X,",
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(vcpu_px_data + i)->bus_master_latency);
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dsdt_line(" 0x%08X,",
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(vcpu_px_data + i)->control);
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dsdt_line(" 0x%08X",
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(vcpu_px_data + i)->status);
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if (i == (vcpu_px_cnt - 1)) {
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dsdt_line(" }");
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} else {
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dsdt_line(" },");
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}
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}
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dsdt_line(" })");
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dsdt_line(" }");
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free(vcpu_px_data);
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}
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void pm_write_dsdt(struct vmctx *ctx, int ncpu)
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{
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int i;
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/* Scope (_PR) */
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dsdt_line("");
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dsdt_line(" Scope (_PR)");
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dsdt_line(" {");
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for (i = 0; i < ncpu; i++) {
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dsdt_line(" Processor (CPU%d, 0x%02X, 0x00000000, 0x00) {}",
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i, i);
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}
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dsdt_line(" }");
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dsdt_line("");
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/* Scope (_PR.CPU(N)) */
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for (i = 0; i < ncpu; i++) {
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dsdt_line(" Scope (_PR.CPU%d)", i);
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dsdt_line(" {");
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dsdt_line("");
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dsdt_write_pss(ctx, i);
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dsdt_write_cst(ctx, i);
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/* hard code _PPC and _PCT for all vpu */
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if (i == 0) {
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dsdt_write_ppc();
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dsdt_write_pct();
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} else {
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dsdt_line(" Method (_PPC, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (^^CPU0._PPC)");
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dsdt_line(" }");
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dsdt_line("");
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dsdt_line(" Method (_PCT, 0, NotSerialized)");
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dsdt_line(" {");
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dsdt_line(" Return (^^CPU0._PCT)");
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dsdt_line(" }");
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dsdt_line("");
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}
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dsdt_line(" }");
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}
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}
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Block a user