hv: More changes to enable GPU passthru

Snoop control is not supported in the graphics VT-d engine and so should
be disabled in the PTEs. Also enabled iommu for graphics in the
dmar_drhd array.

v2: removed disable iommu in handle_one_drhd and combined if cond.
v3: minor code review changes
v4: moved the snoop control change to ept.c to accomodate upstream changes
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
Reviewed-by: Gong Zhipeng <zhipeng.gong@intel.com>
This commit is contained in:
Anitha Chrisanthus
2018-06-12 03:49:05 -07:00
committed by Xie, nanlin
parent 9d4cc5c11d
commit 8d50d40ff8
6 changed files with 11 additions and 12 deletions

View File

@@ -489,7 +489,7 @@ int ept_mmap(struct vm *vm, uint64_t hpa,
* to force snooping of PCIe devices if the page
* is cachable
*/
if ((prot & IA32E_EPT_MT_MASK) != IA32E_EPT_UNCACHED)
if ((prot & IA32E_EPT_MT_MASK) != IA32E_EPT_UNCACHED && iommu_snoop)
prot |= IA32E_EPT_SNOOP_CTRL;
map_mem(&map_params, (void *)hpa,
(void *)gpa, size, prot);

View File

@@ -152,6 +152,8 @@ struct iommu_domain {
uint64_t trans_table_ptr;
};
bool iommu_snoop = true; /* enable iommu snoop control */
static struct list_head dmar_drhd_units;
static uint32_t dmar_hdrh_unit_count;
@@ -419,9 +421,13 @@ static void dmar_register_hrhd(struct dmar_drhd_rt *dmar_uint)
* How to guarantee it when EPT is used as second-level
* translation paging structures?
*/
if (iommu_ecap_sc(dmar_uint->ecap) == 0U)
/* enable snoop control only if it is supported by all the VT-d engines */
if (!iommu_ecap_sc(dmar_uint->ecap)) {
dev_dbg(ACRN_DBG_IOMMU,
"dmar uint doesn't support snoop control!");
iommu_snoop = false;
}
dmar_uint->max_domain_id = iommu_cap_ndoms(dmar_uint->cap) - 1;
@@ -1009,7 +1015,6 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment,
ASSERT(false,
"dmaru doesn't support trans passthrough");
} else {
/* TODO: add Device TLB support */
upper =
DMAR_SET_BITSLICE(upper, CTX_ENTRY_UPPER_AW,
width_to_agaw(