From 8e4e1c96d13ea300e8dc576b6e7a6d0826600fe4 Mon Sep 17 00:00:00 2001 From: Conghui Chen Date: Tue, 13 Aug 2019 13:02:39 +0000 Subject: [PATCH] hv: vuart bugfix for additional byte in tx fifo For communication vuart, when it send data to target vuart's fifo, it should meet the conditions: 1. MCR_LOOPBACK is not set 2. LCR_DLAB is not set 3. access reg is UART16550_THR 4. target_vu is not null But the LCR_DLAB is missed now, and when vuart set it's UART16550_DLL, it will be send to target by mistake as UART16550_DLL = UART16550_THR. Add the missed condition. DLAB in uart16550 spec: Divisor Latch Access Bit. 1 = Allows access to the Divisor Latch Registers and reading of the FIFO Control Register. 0 = Allows access to RBR, THR, IER and IIR registers. Tracked-On: #3681 Signed-off-by: Conghui Chen Reviewed-by: Yin Fengwei Acked-by: Eddie Dong --- hypervisor/dm/vuart.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hypervisor/dm/vuart.c b/hypervisor/dm/vuart.c index f46b41907..d70a66353 100644 --- a/hypervisor/dm/vuart.c +++ b/hypervisor/dm/vuart.c @@ -356,8 +356,8 @@ static bool vuart_write(struct acrn_vcpu *vcpu, uint16_t offset_arg, offset -= vu->port_base; target_vu = vu->target_vu; - if (((vu->mcr & MCR_LOOPBACK) == 0U) && - (offset == UART16550_THR) && (target_vu != NULL)) { + if (((vu->mcr & MCR_LOOPBACK) == 0U) && ((vu->lcr & LCR_DLAB) == 0U) + && (offset == UART16550_THR) && (target_vu != NULL)) { send_to_target(target_vu, value_u8); vuart_lock(vu, rflags); vu->thre_int_pending = true;