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HV: logical and high level precedence expression needs brackets

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Added brackets for expression to make it easy to understand and
reduce the mistake of precedence. The rule is applied to the
mixed same level of prevedence opeartors, high level presedence
operators and logical expression.

Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Yang, Yu-chu
2018-07-18 12:49:28 -07:00
committed by lijinxia
parent 7aec6799a1
commit 91337da5a1
22 changed files with 76 additions and 74 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/include/arch/x86/mmu.h
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@@ -377,7 +377,7 @@ struct e820_entry {
*/
static inline void *mmu_pt_for_pde(uint32_t *pd, uint32_t vaddr)
{
return pd + ((vaddr >> 22U) + 1U) * 1024U;
return pd + (((vaddr >> 22U) + 1U) * 1024U);
}
#define CACHE_FLUSH_INVALIDATE_ALL() \

2
hypervisor/include/arch/x86/vmx.h
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@@ -58,7 +58,7 @@
#define VMX_EOI_EXIT2_HIGH 0x00002021U
#define VMX_EOI_EXIT3_FULL 0x00002022U
#define VMX_EOI_EXIT3_HIGH 0x00002023U
#define VMX_EOI_EXIT(vector) (VMX_EOI_EXIT0_FULL + ((vector) / 64U) * 2U)
#define VMX_EOI_EXIT(vector) (VMX_EOI_EXIT0_FULL + (((vector) / 64U) * 2U))
#define VMX_XSS_EXITING_BITMAP_FULL 0x0000202CU
#define VMX_XSS_EXITING_BITMAP_HIGH 0x0000202DU
/* 64-bit read-only data fields */

4
hypervisor/include/arch/x86/vtd.h
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@@ -91,7 +91,7 @@ static inline uint16_t iommu_cap_fault_reg_offset(uint64_t cap)
static inline uint16_t iommu_cap_max_fault_reg_offset(uint64_t cap)
{
return (iommu_cap_fault_reg_offset(cap) +
iommu_cap_num_fault_regs(cap) * 16U);
(iommu_cap_num_fault_regs(cap) * 16U));
}
static inline uint8_t iommu_cap_zlr(uint64_t cap)
@@ -141,7 +141,7 @@ static inline uint8_t iommu_cap_afl(uint64_t cap)
static inline uint32_t iommu_cap_ndoms(uint64_t cap)
{
return ((1U) << (4U + 2U * ((uint8_t)cap & 0x7U)));
return ((1U) << (4U + (2U * ((uint8_t)cap & 0x7U))));
}
/*

8
hypervisor/include/lib/bits.h
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@@ -178,7 +178,7 @@ static inline uint16_t clz64(uint64_t value)
#define build_bitmap_set(name, op_len, op_type, lock, nr, addr) \
static inline void name(uint16_t nr, volatile op_type *addr) \
{ \
nr = nr & (8U * sizeof(op_type) - 1U); \
nr = nr & ((8U * sizeof(op_type)) - 1U); \
asm volatile(lock "or" op_len " %1,%0" \
: "+m" (*addr) \
: "r" ((op_type)(1UL<<nr)) \
@@ -197,7 +197,7 @@ build_bitmap_set(bitmap32_set, "l", uint32_t, BUS_LOCK, nr, addr)
#define build_bitmap_clear(name, op_len, op_type, lock, nr, addr) \
static inline void name(uint16_t nr, volatile op_type *addr) \
{ \
nr = nr & (8U * sizeof(op_type) - 1U); \
nr = nr & ((8U * sizeof(op_type)) - 1U); \
asm volatile(lock "and" op_len " %1,%0" \
: "+m" (*addr) \
: "r" ((op_type)(~(1UL<<(nr)))) \
@@ -246,7 +246,7 @@ static inline bool bitmap32_test(uint16_t nr, volatile uint32_t *addr)
static inline bool name(uint16_t nr, volatile op_type *addr) \
{ \
int32_t ret=0; \
nr = nr & (8U * sizeof(op_type) - 1U); \
nr = nr & ((8U * sizeof(op_type)) - 1U); \
asm volatile(lock "bts" op_len " %2,%1\n\tsbbl %0,%0" \
: "=r" (ret), "=m" (*addr) \
: "r" ((op_type)nr) \
@@ -269,7 +269,7 @@ build_bitmap_testandset(bitmap32_test_and_set, "l", uint32_t, BUS_LOCK, nr, addr
static inline bool name(uint16_t nr, volatile op_type *addr) \
{ \
int32_t ret=0; \
nr = nr & (8U * sizeof(op_type) - 1U); \
nr = nr & ((8U * sizeof(op_type)) - 1U); \
asm volatile(lock "btr" op_len " %2,%1\n\tsbbl %0,%0" \
: "=r" (ret), "=m" (*addr) \
: "r" ((op_type)nr) \

2
hypervisor/include/lib/rtl.h
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@@ -51,7 +51,7 @@ extern uint32_t tsc_khz;
static inline uint64_t us_to_ticks(uint32_t us)
{
return ((uint64_t)us * (uint64_t)tsc_khz / 1000UL);
return (((uint64_t)us * (uint64_t)tsc_khz) / 1000UL);
}
#define CYCLES_PER_MS us_to_ticks(1000U)