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hv: mmu: cleanup mmu.h

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Remove unused Macro defininion.

Tracked-On: #1124

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Li, Fei1
2018-08-23 16:11:17 +08:00
committed by lijinxia
parent 06ab2b829f
commit 9257ecf4bb
8 changed files with 39 additions and 192 deletions
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6
hypervisor/arch/x86/cpu_primary.S
View File

@@ -225,14 +225,14 @@ cpu_primary32_gdt_ptr:
.align 0x1000
.global cpu_boot32_page_tables_start
cpu_boot32_page_tables_start:
/* 0x3 = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */
/* 0x3 = (PAGE_PRESENT | PAGE_RW) */
.quad cpu_primary32_pdpt_addr + 0x3
/*0x1000 = CPU_PAGE_SIZE*/
.align 0x1000
cpu_primary32_pdpt_addr:
address = 0
.rept 4
/* 0x3 = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */
/* 0x3 = (PAGE_PRESENT | PAGE_RW) */
.quad cpu_primary32_pdt_addr + address + 0x3
/*0x1000 = CPU_PAGE_SIZE*/
address = address + 0x1000
@@ -242,7 +242,7 @@ cpu_primary32_pdpt_addr:
cpu_primary32_pdt_addr:
address = 0
.rept 2048
/* 0x83 = (IA32E_PDPTE_PS_BIT | IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */
/* 0x83 = (PAGE_PSE | PAGE_PRESENT | PAGE_RW) */
.quad address + 0x83
address = address + 0x200000
.endr

6
hypervisor/arch/x86/ept.c
View File

@@ -27,7 +27,7 @@ static uint64_t find_next_table(uint32_t table_offset, const void *table_base)
}
/* Set table present bits to any of the read/write/execute bits */
table_present = (IA32E_EPT_R_BIT | IA32E_EPT_W_BIT | IA32E_EPT_X_BIT);
table_present = EPT_RWX;
/* Determine if a valid entry exists */
if ((table_entry & table_present) == 0UL) {
@@ -274,8 +274,8 @@ int ept_mr_add(const struct vm *vm, uint64_t *pml4_page,
* to force snooping of PCIe devices if the page
* is cachable
*/
if ((prot & IA32E_EPT_MT_MASK) != IA32E_EPT_UNCACHED) {
prot |= IA32E_EPT_SNOOP_CTRL;
if ((prot & EPT_MT_MASK) != EPT_UNCACHED) {
prot |= EPT_SNOOP_CTRL;
}
ret = mmu_add(pml4_page, hpa, gpa, size, prot, PTT_EPT);

12
hypervisor/arch/x86/guest/guest.c
View File

@@ -126,12 +126,12 @@ static int local_gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_inf
}
/* check if the entry present */
if ((entry & MMU_32BIT_PDE_P) == 0U) {
if ((entry & PAGE_PRESENT) == 0U) {
ret = -EFAULT;
goto out;
}
/* check for R/W */
if (pw_info->is_write_access && ((entry & MMU_32BIT_PDE_RW) == 0U)) {
if (pw_info->is_write_access && ((entry & PAGE_RW) == 0U)) {
/* Case1: Supermode and wp is 1
* Case2: Usermode */
if (pw_info->is_user_mode || pw_info->wp) {
@@ -141,16 +141,16 @@ static int local_gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_inf
/* check for nx, since for 32-bit paing, the XD bit is
* reserved(0), use the same logic as PAE/4-level paging */
if (pw_info->is_inst_fetch && pw_info->nxe &&
((entry & MMU_MEM_ATTR_BIT_EXECUTE_DISABLE) != 0U)) {
((entry & PAGE_NX) != 0U)) {
fault = 1;
}
/* check for U/S */
if (((entry & MMU_32BIT_PDE_US) == 0U) && pw_info->is_user_mode) {
if (((entry & PAGE_USER) == 0U) && pw_info->is_user_mode) {
fault = 1;
}
if (pw_info->pse && ((i > 0U) && ((entry & MMU_32BIT_PDE_PS) != 0U))) {
if (pw_info->pse && ((i > 0U) && ((entry & PAGE_PSE) != 0U))) {
break;
}
addr = entry;
@@ -189,7 +189,7 @@ static int local_gva2gpa_pae(struct vcpu *vcpu, struct page_walk_info *pw_info,
index = (gva >> 30) & 0x3UL;
entry = base[index];
if ((entry & MMU_32BIT_PDE_P) == 0U) {
if ((entry & PAGE_PRESENT) == 0U) {
ret = -EFAULT;
goto out;
}

12
hypervisor/arch/x86/mtrr.c
View File

@@ -129,24 +129,24 @@ static uint32_t update_ept(struct vm *vm, uint64_t start,
switch ((uint64_t)type) {
case MTRR_MEM_TYPE_WC:
attr = IA32E_EPT_WC;
attr = EPT_WC;
break;
case MTRR_MEM_TYPE_WT:
attr = IA32E_EPT_WT;
attr = EPT_WT;
break;
case MTRR_MEM_TYPE_WP:
attr = IA32E_EPT_WP;
attr = EPT_WP;
break;
case MTRR_MEM_TYPE_WB:
attr = IA32E_EPT_WB;
attr = EPT_WB;
break;
case MTRR_MEM_TYPE_UC:
default:
attr = IA32E_EPT_UNCACHED;
attr = EPT_UNCACHED;
}
ept_mr_modify(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
start, size, attr, IA32E_EPT_MT_MASK);
start, size, attr, EPT_MT_MASK);
return attr;
}

6
hypervisor/arch/x86/trampoline.S
View File

@@ -203,7 +203,7 @@ CPU_Boot_Page_Tables_ptr:
.align 0x1000
.global CPU_Boot_Page_Tables_Start
CPU_Boot_Page_Tables_Start:
/* 0x3 = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */
/* 0x3 = (PAGE_PRESENT | PAGE_RW) */
.quad trampoline_pdpt_addr + 0x3
/*0x1000 = CPU_PAGE_SIZE*/
.align 0x1000
@@ -211,7 +211,7 @@ CPU_Boot_Page_Tables_Start:
trampoline_pdpt_addr:
address = 0
.rept 4
/* 0x3 = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */
/* 0x3 = (PAGE_PRESENT | PAGE_RW) */
.quad trampoline_pdt_addr + address + 0x3
/*0x1000 = CPU_PAGE_SIZE*/
address = address + 0x1000
@@ -221,7 +221,7 @@ trampoline_pdpt_addr:
trampoline_pdt_addr:
address = 0
.rept 2048
/* 0x83 = (IA32E_PDPTE_PS_BIT | IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */
/* 0x83 = (PAGE_PSE | PAGE_PRESENT | PAGE_RW) */
.quad address + 0x83
address = address + 0x200000
.endr

2
hypervisor/arch/x86/trusty.c
View File

@@ -119,7 +119,7 @@ static void create_secure_world_ept(struct vm *vm, uint64_t gpa_orig,
for (i = 0U; i < IA32E_NUM_ENTRIES - 1; i++) {
pdpte = mem_read64(src_pdpte_p);
if ((pdpte & table_present) != 0UL) {
pdpte &= ~IA32E_EPT_X_BIT;
pdpte &= ~EPT_EXE;
mem_write64(dest_pdpte_p, pdpte);
}
src_pdpte_p++;