github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-21 05:02:24 +00:00
Code Issues Projects Releases Wiki Activity

hv: mmu: cleanup mmu.h

Browse Source 
Remove unused Macro defininion.

Tracked-On: #1124

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Li, Fei1 2018-08-23 16:11:17 +08:00 committed by lijinxia
parent 06ab2b829f
commit 9257ecf4bb
8 changed files with 39 additions and 192 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
hypervisor/arch/x86/cpu_primary.S
View File

@ -225,14 +225,14 @@ cpu_primary32_gdt_ptr:
.align 0x1000 .align 0x1000
.global cpu_boot32_page_tables_start .global cpu_boot32_page_tables_start
cpu_boot32_page_tables_start: cpu_boot32_page_tables_start:
/* 0x3 = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */ /* 0x3 = (PAGE_PRESENT | PAGE_RW) */
.quad cpu_primary32_pdpt_addr + 0x3 .quad cpu_primary32_pdpt_addr + 0x3
/*0x1000 = CPU_PAGE_SIZE*/ /*0x1000 = CPU_PAGE_SIZE*/
.align 0x1000 .align 0x1000
cpu_primary32_pdpt_addr: cpu_primary32_pdpt_addr:
address = 0 address = 0
.rept 4 .rept 4
/* 0x3 = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */ /* 0x3 = (PAGE_PRESENT | PAGE_RW) */
.quad cpu_primary32_pdt_addr + address + 0x3 .quad cpu_primary32_pdt_addr + address + 0x3
/*0x1000 = CPU_PAGE_SIZE*/ /*0x1000 = CPU_PAGE_SIZE*/
address = address + 0x1000 address = address + 0x1000
@ -242,7 +242,7 @@ cpu_primary32_pdpt_addr:
cpu_primary32_pdt_addr: cpu_primary32_pdt_addr:
address = 0 address = 0
.rept 2048 .rept 2048
/* 0x83 = (IA32E_PDPTE_PS_BIT | IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */ /* 0x83 = (PAGE_PSE | PAGE_PRESENT | PAGE_RW) */
.quad address + 0x83 .quad address + 0x83
address = address + 0x200000 address = address + 0x200000
.endr .endr

6
hypervisor/arch/x86/ept.c
View File

@ -27,7 +27,7 @@ static uint64_t find_next_table(uint32_t table_offset, const void *table_base)
} }
/* Set table present bits to any of the read/write/execute bits */ /* Set table present bits to any of the read/write/execute bits */
table_present = (IA32E_EPT_R_BIT | IA32E_EPT_W_BIT | IA32E_EPT_X_BIT); table_present = EPT_RWX;
/* Determine if a valid entry exists */ /* Determine if a valid entry exists */
if ((table_entry & table_present) == 0UL) { if ((table_entry & table_present) == 0UL) {
@ -274,8 +274,8 @@ int ept_mr_add(const struct vm *vm, uint64_t *pml4_page,
* to force snooping of PCIe devices if the page * to force snooping of PCIe devices if the page
* is cachable * is cachable
*/ */
if ((prot & IA32E_EPT_MT_MASK) != IA32E_EPT_UNCACHED) { if ((prot & EPT_MT_MASK) != EPT_UNCACHED) {
prot |= IA32E_EPT_SNOOP_CTRL; prot |= EPT_SNOOP_CTRL;
} }
ret = mmu_add(pml4_page, hpa, gpa, size, prot, PTT_EPT); ret = mmu_add(pml4_page, hpa, gpa, size, prot, PTT_EPT);

12
hypervisor/arch/x86/guest/guest.c
View File

@ -126,12 +126,12 @@ static int local_gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_inf
} }
/* check if the entry present */ /* check if the entry present */
if ((entry & MMU_32BIT_PDE_P) == 0U) { if ((entry & PAGE_PRESENT) == 0U) {
ret = -EFAULT; ret = -EFAULT;
goto out; goto out;
} }
/* check for R/W */ /* check for R/W */
if (pw_info->is_write_access && ((entry & MMU_32BIT_PDE_RW) == 0U)) { if (pw_info->is_write_access && ((entry & PAGE_RW) == 0U)) {
/* Case1: Supermode and wp is 1 /* Case1: Supermode and wp is 1
* Case2: Usermode */ * Case2: Usermode */
if (pw_info->is_user_mode || pw_info->wp) { if (pw_info->is_user_mode || pw_info->wp) {
@ -141,16 +141,16 @@ static int local_gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_inf
/* check for nx, since for 32-bit paing, the XD bit is /* check for nx, since for 32-bit paing, the XD bit is
* reserved(0), use the same logic as PAE/4-level paging */ * reserved(0), use the same logic as PAE/4-level paging */
if (pw_info->is_inst_fetch && pw_info->nxe && if (pw_info->is_inst_fetch && pw_info->nxe &&
((entry & MMU_MEM_ATTR_BIT_EXECUTE_DISABLE) != 0U)) { ((entry & PAGE_NX) != 0U)) {
fault = 1; fault = 1;
} }
/* check for U/S */ /* check for U/S */
if (((entry & MMU_32BIT_PDE_US) == 0U) && pw_info->is_user_mode) { if (((entry & PAGE_USER) == 0U) && pw_info->is_user_mode) {
fault = 1; fault = 1;
} }
if (pw_info->pse && ((i > 0U) && ((entry & MMU_32BIT_PDE_PS) != 0U))) { if (pw_info->pse && ((i > 0U) && ((entry & PAGE_PSE) != 0U))) {
break; break;
} }
addr = entry; addr = entry;
@ -189,7 +189,7 @@ static int local_gva2gpa_pae(struct vcpu *vcpu, struct page_walk_info *pw_info,
index = (gva >> 30) & 0x3UL; index = (gva >> 30) & 0x3UL;
entry = base[index]; entry = base[index];
if ((entry & MMU_32BIT_PDE_P) == 0U) { if ((entry & PAGE_PRESENT) == 0U) {
ret = -EFAULT; ret = -EFAULT;
goto out; goto out;
} }

12
hypervisor/arch/x86/mtrr.c
View File

@ -129,24 +129,24 @@ static uint32_t update_ept(struct vm *vm, uint64_t start,
switch ((uint64_t)type) { switch ((uint64_t)type) {
case MTRR_MEM_TYPE_WC: case MTRR_MEM_TYPE_WC:
attr = IA32E_EPT_WC; attr = EPT_WC;
break; break;
case MTRR_MEM_TYPE_WT: case MTRR_MEM_TYPE_WT:
attr = IA32E_EPT_WT; attr = EPT_WT;
break; break;
case MTRR_MEM_TYPE_WP: case MTRR_MEM_TYPE_WP:
attr = IA32E_EPT_WP; attr = EPT_WP;
break; break;
case MTRR_MEM_TYPE_WB: case MTRR_MEM_TYPE_WB:
attr = IA32E_EPT_WB; attr = EPT_WB;
break; break;
case MTRR_MEM_TYPE_UC: case MTRR_MEM_TYPE_UC:
default: default:
attr = IA32E_EPT_UNCACHED; attr = EPT_UNCACHED;
} }
ept_mr_modify(vm, (uint64_t *)vm->arch_vm.nworld_eptp, ept_mr_modify(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
start, size, attr, IA32E_EPT_MT_MASK); start, size, attr, EPT_MT_MASK);
return attr; return attr;
} }

6
hypervisor/arch/x86/trampoline.S
View File

@ -203,7 +203,7 @@ CPU_Boot_Page_Tables_ptr:
.align 0x1000 .align 0x1000
.global CPU_Boot_Page_Tables_Start .global CPU_Boot_Page_Tables_Start
CPU_Boot_Page_Tables_Start: CPU_Boot_Page_Tables_Start:
/* 0x3 = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */ /* 0x3 = (PAGE_PRESENT | PAGE_RW) */
.quad trampoline_pdpt_addr + 0x3 .quad trampoline_pdpt_addr + 0x3
/*0x1000 = CPU_PAGE_SIZE*/ /*0x1000 = CPU_PAGE_SIZE*/
.align 0x1000 .align 0x1000
@ -211,7 +211,7 @@ CPU_Boot_Page_Tables_Start:
trampoline_pdpt_addr: trampoline_pdpt_addr:
address = 0 address = 0
.rept 4 .rept 4
/* 0x3 = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */ /* 0x3 = (PAGE_PRESENT | PAGE_RW) */
.quad trampoline_pdt_addr + address + 0x3 .quad trampoline_pdt_addr + address + 0x3
/*0x1000 = CPU_PAGE_SIZE*/ /*0x1000 = CPU_PAGE_SIZE*/
address = address + 0x1000 address = address + 0x1000
@ -221,7 +221,7 @@ trampoline_pdpt_addr:
trampoline_pdt_addr: trampoline_pdt_addr:
address = 0 address = 0
.rept 2048 .rept 2048
/* 0x83 = (IA32E_PDPTE_PS_BIT | IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT) */ /* 0x83 = (PAGE_PSE | PAGE_PRESENT | PAGE_RW) */
.quad address + 0x83 .quad address + 0x83
address = address + 0x200000 address = address + 0x200000
.endr .endr

2
hypervisor/arch/x86/trusty.c
View File

@ -119,7 +119,7 @@ static void create_secure_world_ept(struct vm *vm, uint64_t gpa_orig,
for (i = 0U; i < IA32E_NUM_ENTRIES - 1; i++) { for (i = 0U; i < IA32E_NUM_ENTRIES - 1; i++) {
pdpte = mem_read64(src_pdpte_p); pdpte = mem_read64(src_pdpte_p);
if ((pdpte & table_present) != 0UL) { if ((pdpte & table_present) != 0UL) {
pdpte &= ~IA32E_EPT_X_BIT; pdpte &= ~EPT_EXE;
mem_write64(dest_pdpte_p, pdpte); mem_write64(dest_pdpte_p, pdpte);
} }
src_pdpte_p++; src_pdpte_p++;

154
hypervisor/include/arch/x86/mmu.h
View File

@ -10,83 +10,24 @@
/* Size of all page-table entries (in bytes) */ /* Size of all page-table entries (in bytes) */
#define IA32E_COMM_ENTRY_SIZE 8U #define IA32E_COMM_ENTRY_SIZE 8U
/* Definitions common for all IA-32e related paging entries */
#define IA32E_COMM_P_BIT 0x0000000000000001UL
#define IA32E_COMM_RW_BIT 0x0000000000000002UL
#define IA32E_COMM_US_BIT 0x0000000000000004UL
#define IA32E_COMM_PWT_BIT 0x0000000000000008UL
#define IA32E_COMM_PCD_BIT 0x0000000000000010UL
#define IA32E_COMM_A_BIT 0x0000000000000020UL
#define IA32E_COMM_XD_BIT 0x8000000000000000UL
/* Defines for EPT paging entries */
#define IA32E_EPT_R_BIT 0x0000000000000001UL
#define IA32E_EPT_W_BIT 0x0000000000000002UL
#define IA32E_EPT_X_BIT 0x0000000000000004UL
#define IA32E_EPT_UNCACHED (0UL<<3)
#define IA32E_EPT_WC (1UL<<3)
#define IA32E_EPT_WT (4UL<<3)
#define IA32E_EPT_WP (5UL<<3)
#define IA32E_EPT_WB (6UL<<3)
#define IA32E_EPT_MT_MASK (7UL<<3)
#define IA32E_EPT_PAT_IGNORE 0x0000000000000040UL
#define IA32E_EPT_ACCESS_FLAG 0x0000000000000100UL
#define IA32E_EPT_DIRTY_FLAG 0x0000000000000200UL
#define IA32E_EPT_SNOOP_CTRL 0x0000000000000800UL
#define IA32E_EPT_SUPPRESS_VE 0x8000000000000000UL
/* Definitions common or ignored for all IA-32e related paging entries */
#define IA32E_COMM_D_BIT 0x0000000000000040UL
#define IA32E_COMM_G_BIT 0x0000000000000100UL
/* Definitions exclusive to a Page Map Level 4 Entry (PML4E) */
#define IA32E_PML4E_INDEX_MASK_START 39
#define IA32E_PML4E_ADDR_MASK 0x0000FF8000000000UL
/* Definitions exclusive to a Page Directory Pointer Table Entry (PDPTE) */ /* Definitions exclusive to a Page Directory Pointer Table Entry (PDPTE) */
#define IA32E_PDPTE_D_BIT 0x0000000000000040UL #define IA32E_PDPTE_D_BIT 0x0000000000000040UL
#define IA32E_PDPTE_PS_BIT 0x0000000000000080UL #define IA32E_PDPTE_PS_BIT 0x0000000000000080UL
#define IA32E_PDPTE_PAT_BIT 0x0000000000001000UL #define IA32E_PDPTE_PAT_BIT 0x0000000000001000UL
#define IA32E_PDPTE_ADDR_MASK 0x0000FFFFC0000000UL #define IA32E_PDPTE_ADDR_MASK 0x0000FFFFC0000000UL
#define IA32E_PDPTE_INDEX_MASK_START \
(IA32E_PML4E_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
/* Definitions exclusive to a Page Directory Entry (PDE) 1G or 2M */ /* Definitions exclusive to a Page Directory Entry (PDE) 1G or 2M */
#define IA32E_PDE_D_BIT 0x0000000000000040UL #define IA32E_PDE_D_BIT 0x0000000000000040UL
#define IA32E_PDE_PS_BIT 0x0000000000000080UL #define IA32E_PDE_PS_BIT 0x0000000000000080UL
#define IA32E_PDE_PAT_BIT 0x0000000000001000UL #define IA32E_PDE_PAT_BIT 0x0000000000001000UL
#define IA32E_PDE_ADDR_MASK 0x0000FFFFFFE00000UL #define IA32E_PDE_ADDR_MASK 0x0000FFFFFFE00000UL
#define IA32E_PDE_INDEX_MASK_START \
(IA32E_PDPTE_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
/* Definitions exclusive to Page Table Entries (PTE) */ /* Definitions exclusive to Page Table Entries (PTE) */
#define IA32E_PTE_D_BIT 0x0000000000000040UL #define IA32E_PTE_D_BIT 0x0000000000000040UL
#define IA32E_PTE_PAT_BIT 0x0000000000000080UL #define IA32E_PTE_PAT_BIT 0x0000000000000080UL
#define IA32E_PTE_G_BIT 0x0000000000000100UL #define IA32E_PTE_G_BIT 0x0000000000000100UL
#define IA32E_PTE_ADDR_MASK 0x0000FFFFFFFFF000UL #define IA32E_PTE_ADDR_MASK 0x0000FFFFFFFFF000UL
#define IA32E_PTE_INDEX_MASK_START \
(IA32E_PDE_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
/** The 'Present' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_P 0x00000001U
/** The 'Read/Write' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_RW 0x00000002U
/** The 'User/Supervisor' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_US 0x00000004U
/** The 'Page Write Through' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_PWT 0x00000008U
/** The 'Page Cache Disable' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_PCD 0x00000010U
/** The 'Accessed' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_A 0x00000020U
/** The 'Dirty' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_D 0x00000040U
/** The 'Page Size' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_PS 0x00000080U
/** The 'Global' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_G 0x00000100U
/** The 'PAT' bit in a page 32 bit paging directory entry */
#define MMU_32BIT_PDE_PAT 0x00001000U
/** The flag that indicates that the page fault was caused by a non present /** The flag that indicates that the page fault was caused by a non present
* page. * page.
*/ */
@ -108,29 +49,9 @@
#define MEM_1K 1024U #define MEM_1K 1024U
#define MEM_2K (MEM_1K * 2U) #define MEM_2K (MEM_1K * 2U)
#define MEM_4K (MEM_1K * 4U) #define MEM_4K (MEM_1K * 4U)
#define MEM_8K (MEM_1K * 8U)
#define MEM_16K (MEM_1K * 16U)
#define MEM_32K (MEM_1K * 32U)
#define MEM_64K (MEM_1K * 64U)
#define MEM_128K (MEM_1K * 128U)
#define MEM_256K (MEM_1K * 256U)
#define MEM_512K (MEM_1K * 512U)
#define MEM_1M (MEM_1K * 1024U) #define MEM_1M (MEM_1K * 1024U)
#define MEM_2M (MEM_1M * 2U) #define MEM_2M (MEM_1M * 2U)
#define MEM_4M (MEM_1M * 4U)
#define MEM_8M (MEM_1M * 8U)
#define MEM_16M (MEM_1M * 16U)
#define MEM_32M (MEM_1M * 32U)
#define MEM_64M (MEM_1M * 64U)
#define MEM_128M (MEM_1M * 128U)
#define MEM_256M (MEM_1M * 256U)
#define MEM_512M (MEM_1M * 512U)
#define MEM_1G (MEM_1M * 1024U) #define MEM_1G (MEM_1M * 1024U)
#define MEM_2G (MEM_1G * 2U)
#define MEM_3G (MEM_1G * 3U)
#define MEM_4G (MEM_1G * 4U)
#define MEM_5G (MEM_1G * 5U)
#define MEM_6G (MEM_1G * 6U)
#ifndef ASSEMBLER #ifndef ASSEMBLER
@ -139,76 +60,10 @@
/* Define cache line size (in bytes) */ /* Define cache line size (in bytes) */
#define CACHE_LINE_SIZE 64U #define CACHE_LINE_SIZE 64U
/* Size of all page structures for IA-32e */
#define IA32E_STRUCT_SIZE MEM_4K
/* IA32E Paging constants */ /* IA32E Paging constants */
#define IA32E_INDEX_MASK_BITS 9
#define IA32E_NUM_ENTRIES 512U #define IA32E_NUM_ENTRIES 512U
#define IA32E_INDEX_MASK (uint64_t)(IA32E_NUM_ENTRIES - 1U)
#define IA32E_REF_MASK \ #define IA32E_REF_MASK \
(boot_cpu_data.physical_address_mask) (boot_cpu_data.physical_address_mask)
#define IA32E_FIRST_BLOCK_INDEX 1
/* Macro to get PML4 index given an address */
#define IA32E_PML4E_INDEX_CALC(address) \
(uint32_t)((((uint64_t)address >> IA32E_PML4E_INDEX_MASK_START) & \
IA32E_INDEX_MASK) * sizeof(uint64_t))
/* Macro to get PDPT index given an address */
#define IA32E_PDPTE_INDEX_CALC(address) \
(uint32_t)((((uint64_t)address >> IA32E_PDPTE_INDEX_MASK_START) & \
IA32E_INDEX_MASK) * sizeof(uint64_t))
/* Macro to get PD index given an address */
#define IA32E_PDE_INDEX_CALC(address) \
(uint32_t)((((uint64_t)address >> IA32E_PDE_INDEX_MASK_START) & \
IA32E_INDEX_MASK) * sizeof(uint64_t))
/* Macro to get PT index given an address */
#define IA32E_PTE_INDEX_CALC(address) \
(uint32_t)((((uint64_t)address >> IA32E_PTE_INDEX_MASK_START) & \
IA32E_INDEX_MASK) * sizeof(uint64_t))
/* Macro to obtain a 2 MB page offset from given linear address */
#define IA32E_GET_2MB_PG_OFFSET(address) \
(address & 0x001FFFFF)
/* Macro to obtain a 4KB page offset from given linear address */
#define IA32E_GET_4KB_PG_OFFSET(address) \
(address & 0x00000FFF)
/*
* The following generic attributes MMU_MEM_ATTR_FLAG_xxx may be OR'd with one
* and only one of the MMU_MEM_ATTR_TYPE_xxx definitions
*/
/* Definitions for memory types related to x64 */
#define MMU_MEM_ATTR_BIT_READ_WRITE IA32E_COMM_RW_BIT
#define MMU_MEM_ATTR_BIT_USER_ACCESSIBLE IA32E_COMM_US_BIT
#define MMU_MEM_ATTR_BIT_EXECUTE_DISABLE IA32E_COMM_XD_BIT
/* Selection of Page Attribute Table (PAT) entries with PAT, PCD and PWT
* encoding. See also pat.h
*/
/* Selects PAT0 WB */
#define MMU_MEM_ATTR_TYPE_CACHED_WB (0x0000000000000000UL)
/* Selects PAT1 WT */
#define MMU_MEM_ATTR_TYPE_CACHED_WT (IA32E_COMM_PWT_BIT)
/* Selects PAT2 UCM */
#define MMU_MEM_ATTR_TYPE_UNCACHED_MINUS (IA32E_COMM_PCD_BIT)
/* Selects PAT3 UC */
#define MMU_MEM_ATTR_TYPE_UNCACHED \
(IA32E_COMM_PCD_BIT | IA32E_COMM_PWT_BIT)
/* Selects PAT6 WC */
#define MMU_MEM_ATTR_TYPE_WRITE_COMBINED \
(IA32E_PDPTE_PAT_BIT | IA32E_COMM_PCD_BIT)
/* Selects PAT7 WP */
#define MMU_MEM_ATTR_TYPE_WRITE_PROTECTED \
(IA32E_PDPTE_PAT_BIT | IA32E_COMM_PCD_BIT | IA32E_COMM_PWT_BIT)
/* memory type bits mask */
#define MMU_MEM_ATTR_TYPE_MASK \
(IA32E_PDPTE_PAT_BIT | IA32E_COMM_PCD_BIT | IA32E_COMM_PWT_BIT)
#define ROUND_PAGE_UP(addr) \ #define ROUND_PAGE_UP(addr) \
((((addr) + (uint64_t)CPU_PAGE_SIZE) - 1UL) & CPU_PAGE_MASK) ((((addr) + (uint64_t)CPU_PAGE_SIZE) - 1UL) & CPU_PAGE_MASK)
@ -217,7 +72,6 @@
enum _page_table_type { enum _page_table_type {
PTT_PRIMARY = 0, /* Mapping for hypervisor */ PTT_PRIMARY = 0, /* Mapping for hypervisor */
PTT_EPT = 1, PTT_EPT = 1,
PAGETABLE_TYPE_UNKNOWN,
}; };
/* Represent the 4 levels of translation tables in IA-32e paging mode */ /* Represent the 4 levels of translation tables in IA-32e paging mode */
@ -226,14 +80,6 @@ enum _page_table_level {
IA32E_PDPT = 1, IA32E_PDPT = 1,
IA32E_PD = 2, IA32E_PD = 2,
IA32E_PT = 3, IA32E_PT = 3,
IA32E_UNKNOWN,
};
/* Page table entry present */
enum _page_table_present {
PT_NOT_PRESENT = 0,
PT_PRESENT = 1,
PT_MISCFG_PRESENT = 2,
}; };
/* Page size */ /* Page size */

1
hypervisor/include/arch/x86/pgtable_types.h
View File

@ -38,6 +38,7 @@
#define EPT_WP (5UL << EPT_MT_SHIFT) #define EPT_WP (5UL << EPT_MT_SHIFT)
#define EPT_WB (6UL << EPT_MT_SHIFT) #define EPT_WB (6UL << EPT_MT_SHIFT)
#define EPT_MT_MASK (7UL << EPT_MT_SHIFT) #define EPT_MT_MASK (7UL << EPT_MT_SHIFT)
/* VTD: Second-Level Paging Entries: Snoop Control */
#define EPT_SNOOP_CTRL (1UL << 11U) #define EPT_SNOOP_CTRL (1UL << 11U)
#define EPT_VE (1UL << 63U) #define EPT_VE (1UL << 63U)