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HV: Add MBA support in ACRN

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This patch adds RDT MBA support to detect, configure and
and setup MBA throttle registers based on VM configuration.

Tracked-On: #3725
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Vijay Dhanraj
2020-02-28 13:48:33 -08:00
committed by Eddie Dong
parent d54d35efe5
commit 92ee33b035
4 changed files with 100 additions and 21 deletions
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2
hypervisor/include/arch/x86/board.h
View File

@@ -15,6 +15,7 @@
struct acrn_vm;
struct platform_clos_info {
uint16_t mba_delay;
uint32_t clos_mask;
uint32_t msr_index;
};
@@ -24,6 +25,7 @@ extern struct dmar_info plat_dmar_info;
#ifdef CONFIG_RDT_ENABLED
extern struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
extern struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
extern struct platform_clos_info platform_mba_clos_array[MAX_PLATFORM_CLOS_NUM];
#endif
extern const struct cpu_state_table board_cpu_state_tbl;

1
hypervisor/include/arch/x86/msr.h
View File

@@ -341,6 +341,7 @@
#define MSR_IA32_PM_CTL1 0x00000DB1U
#define MSR_IA32_THREAD_STALL 0x00000DB2U
#define MSR_IA32_L2_MASK_BASE 0x00000D10U
#define MSR_IA32_MBA_MASK_BASE 0x00000D50U
#define MSR_IA32_BNDCFGS 0x00000D90U
#define MSR_IA32_EFER 0xC0000080U
#define MSR_IA32_STAR 0xC0000081U

21
hypervisor/include/arch/x86/rdt.h
View File

@@ -10,21 +10,34 @@
enum {
RDT_RESOURCE_L3,
RDT_RESOURCE_L2,
RDT_RESOURCE_MBA,
/* Must be the last */
RDT_NUM_RESOURCES,
};
#define RDT_RESID_L3 1U
#define RDT_RESID_L2 2U
#define RDT_RESID_L3 1U
#define RDT_RESID_L2 2U
#define RDT_RESID_MBA 3U
extern const uint16_t hv_clos;
extern const uint16_t platform_clos_num;
struct rdt_cache {
uint32_t bitmask; /* A bitmask where each set bit indicates the corresponding cache way
may be used by other entities in the platform (e.g. GPU) */
uint16_t cbm_len; /* Length of Cache mask in bits */
};
struct rdt_membw {
uint16_t mba_max; /* Max MBA delay throttling value supported */
bool delay_linear; /* True if memory B/W delay is in linear scale */
};
/* The intel Resource Director Tech(RDT) based Allocation Tech support */
struct rdt_info {
uint32_t bitmask; /* Shared CLOS bitmask used by other entities */
uint16_t cbm_len; /* Length of Cache mask in bits */
struct rdt_cache cache;
struct rdt_membw membw;
uint16_t clos_max; /* Maximum CLOS supported, 0 indicates resource is not supported.*/
uint32_t res_id;
uint32_t msr_base; /* MSR base to program clos mask*/