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HV: Prepare cpu_secondary.S for AP trampoline code relocation

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V1->V2: removed CONFIG_LOW_RAM_START and added ".org 0" to
cpu_secondary.S

The assumption is trampoline code is relocated while HV is not, so:

trampoline code is built at address 0, and CS register is updated
by SIPI to reflect the correct vector

in real mode part, added extra pointers for page tables and long jump buffer
so it's possible for HV code to patch the relocation offset

in long mode part, use absolute addressing when referring HV symbols,
and use relative addressing for symbols within trampoline code

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
This commit is contained in:
Zide Chen
2018-05-02 23:09:19 -07:00
committed by Jack Ren
parent 8c06b69622
commit 9323f811ea
4 changed files with 25 additions and 16 deletions
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1
hypervisor/bsp/sbl/include/bsp/bsp_cfg.h
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@@ -41,7 +41,6 @@
#define HEAP_SIZE 0x100000
#define CONSOLE_LOGLEVEL_DEFAULT 2
#define MEM_LOGLEVEL_DEFAULT 4
#define CONFIG_LOW_RAM_START 0x00001000
#define CONFIG_LOW_RAM_SIZE 0x000CF000
#define CONFIG_RAM_START 0x6E000000
#define CONFIG_RAM_SIZE 0x02000000 /* 32M */