github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2026-06-06 09:06:30 +00:00
Code Issues Projects Releases Wiki Activity

hv: code style fix for partition mode specific code

Browse Source 
There are still some misra-c violations when CONFIG_PARTITION_MODE is defined.

arch/x86/configs:
- remove the unused macro: PRE_LAUNCH_VM_NUM
- pt_dev.c: VMx_CONFIG_PCI_PTDEV_NUM has been defined in partition_config.h,
  should not hard code them again in pt_dev.c.
- ve820.c: use "UL" suffix instead of "U" for 64 bits variables.

vmid is uint16_t in ACRN, so vuart_vmid should be uint16_t as well.

Fix another few other miscellaneous misra-c violations.

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Zide Chen
2019-02-19 09:10:04 -08:00
committed by Eddie Dong
parent 8478a328a3
commit 94e1227559
10 changed files with 47 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/arch/x86/configs/dnv-cb2/partition_config.h
View File

@@ -7,8 +7,6 @@
#ifndef PARTITION_CONFIG_H
#define PARTITION_CONFIG_H
#define PRE_LAUNCH_VM_NUM 2
#define VM0_CONFIGURED
#define VM0_CONFIG_NAME "PRE-LAUNCHED VM1 for DNV-CB2"

5
hypervisor/arch/x86/configs/dnv-cb2/pt_dev.c
View File

@@ -5,8 +5,9 @@
*/
#include <vm.h>
#include <partition_config.h>
struct acrn_vm_pci_ptdev_config vm0_pci_ptdevs[3] = {
struct acrn_vm_pci_ptdev_config vm0_pci_ptdevs[VM0_CONFIG_PCI_PTDEV_NUM] = {
{
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
.pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
@@ -21,7 +22,7 @@ struct acrn_vm_pci_ptdev_config vm0_pci_ptdevs[3] = {
},
};
struct acrn_vm_pci_ptdev_config vm1_pci_ptdevs[3] = {
struct acrn_vm_pci_ptdev_config vm1_pci_ptdevs[VM1_CONFIG_PCI_PTDEV_NUM] = {
{
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
.pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},

30
hypervisor/arch/x86/configs/dnv-cb2/ve820.c
View File

@@ -8,32 +8,32 @@
const struct e820_entry ve820_entry[E820_MAX_ENTRIES] = {
{ /* 0 to mptable */
.baseaddr = 0x0U,
.length = 0xEFFFFU,
.type = E820_TYPE_RAM
.baseaddr = 0x0UL,
.length = 0xEFFFFUL,
.type = E820_TYPE_RAM
},
{ /* mptable 65536U */
.baseaddr = 0xF0000U,
.length = 0x10000U,
.type = E820_TYPE_RESERVED
.baseaddr = 0xF0000UL,
.length = 0x10000UL,
.type = E820_TYPE_RESERVED
},
{ /* mptable to lowmem */
.baseaddr = 0x100000U,
.length = 0x7FF00000U,
.type = E820_TYPE_RAM
.baseaddr = 0x100000UL,
.length = 0x7FF00000UL,
.type = E820_TYPE_RAM
},
{ /* lowmem to PCI hole */
.baseaddr = 0x80000000U,
.length = 0x40000000U,
.type = E820_TYPE_RESERVED
.baseaddr = 0x80000000UL,
.length = 0x40000000UL,
.type = E820_TYPE_RESERVED
},
{ /* PCI hole to 4G */
.baseaddr = 0xe0000000U,
.length = 0x20000000U,
.type = E820_TYPE_RESERVED
.baseaddr = 0xe0000000UL,
.length = 0x20000000UL,
.type = E820_TYPE_RESERVED
},
};