mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-21 21:19:35 +00:00
fix "function return type inconsistent"
MISRA C required function return type should be consistented. Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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1a607b669d
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9600dfa07d
@ -77,7 +77,7 @@ inline bool cpu_has_cap(uint32_t bit)
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if (feat_idx >= FEATURE_WORDS)
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return false;
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return !!(boot_cpu_data.cpuid_leaves[feat_idx] & (1 << feat_bit));
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return ((boot_cpu_data.cpuid_leaves[feat_idx] & (1 << feat_bit)) != 0U);
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}
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static inline bool get_monitor_cap(void)
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@ -250,7 +250,7 @@ static void alloc_phy_cpu_data(uint16_t pcpu_num)
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ASSERT(per_cpu_data_base_ptr != NULL, "");
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}
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int __attribute__((weak)) parse_madt(uint8_t *lapic_id_base)
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uint16_t __attribute__((weak)) parse_madt(uint8_t *lapic_id_base)
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{
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static const uint32_t lapic_id[] = {0, 2, 4, 6};
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uint32_t i;
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@ -163,9 +163,9 @@ uint64_t hpa2gpa(struct vm *vm, uint64_t hpa)
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| (hpa & (entry.page_size - 1)));
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}
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int is_ept_supported(void)
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bool is_ept_supported(void)
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{
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uint16_t status;
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bool status;
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uint64_t tmp64;
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/* Read primary processor based VM control. */
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@ -179,14 +179,14 @@ int is_ept_supported(void)
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/* Check if EPT is supported. */
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if ((tmp64 & (((uint64_t)VMX_PROCBASED_CTLS2_EPT) << 32)) != 0U) {
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/* EPT is present. */
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status = 1;
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status = true;
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} else {
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status = 0;
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status = false;
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}
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} else {
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/* Secondary processor based VM control is not present */
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status = 0;
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status = false;
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}
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return status;
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@ -109,12 +109,12 @@ static inline void inv_tlb_one_page(void *addr)
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static inline bool cpu_has_vmx_ept_cap(uint32_t bit_mask)
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{
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return !!(vmx_caps.ept & bit_mask);
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return ((vmx_caps.ept & bit_mask) != 0U);
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}
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static inline bool cpu_has_vmx_vpid_cap(uint32_t bit_mask)
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{
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return !!(vmx_caps.vpid & bit_mask);
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return ((vmx_caps.vpid & bit_mask) != 0U);
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}
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int check_vmx_mmu_cap(void)
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@ -1201,7 +1201,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
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}
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/* Check for EPT support */
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if (is_ept_supported() != 0)
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if (is_ept_supported())
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pr_dbg("EPT is supported");
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else
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pr_err("Error: EPT is not supported");
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@ -32,9 +32,9 @@ void release_schedule_lock(uint16_t pcpu_id)
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spinlock_release(&per_cpu(sched_ctx, pcpu_id).scheduler_lock);
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}
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int allocate_pcpu(void)
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uint16_t allocate_pcpu(void)
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{
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int i;
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uint16_t i;
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for (i = 0; i < phys_cpu_num; i++) {
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if (bitmap_test_and_set(i, &pcpu_used_bitmap) == 0)
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@ -37,7 +37,7 @@ static inline uint32_t sbuf_calculate_allocate_size(uint32_t ele_num,
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return 0;
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}
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return sbuf_allocate_size;
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return (uint32_t) sbuf_allocate_size;
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}
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struct shared_buf *sbuf_allocate(uint32_t ele_num, uint32_t ele_size)
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@ -98,7 +98,7 @@ static int fifo_numchars(struct fifo *fifo)
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*
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* Return an interrupt reason if one is available.
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*/
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static int uart_intr_reason(struct vuart *vu)
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static uint8_t uart_intr_reason(struct vuart *vu)
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{
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if ((vu->lsr & LSR_OE) != 0 && (vu->ier & IER_ELSI) != 0)
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return IIR_RLS;
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@ -131,7 +131,7 @@ static void uart_init(struct vuart *vu)
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*/
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static void uart_toggle_intr(struct vuart *vu)
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{
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char intr_reason;
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uint8_t intr_reason;
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intr_reason = uart_intr_reason(vu);
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@ -229,7 +229,8 @@ static uint32_t uart_read(__unused struct vm_io_handler *hdlr,
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struct vm *vm, uint16_t offset,
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__unused size_t width)
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{
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char iir, intr_reason, reg;
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char iir, reg;
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uint8_t intr_reason;
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struct vuart *vu = vm_vuart(vm);
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offset -= vu->base;
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vuart_lock(vu);
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@ -363,7 +363,7 @@ static inline void clflush(volatile void *p)
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extern uint8_t CPU_Boot_Page_Tables_Start_VM[];
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/* External Interfaces */
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int is_ept_supported(void);
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bool is_ept_supported(void);
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uint64_t create_guest_initial_paging(struct vm *vm);
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void destroy_ept(struct vm *vm);
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uint64_t gpa2hpa(struct vm *vm, uint64_t gpa);
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@ -425,7 +425,7 @@ static inline uint8_t get_vcpu_mode(struct vcpu *vcpu)
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static inline bool cpu_has_vmx_unrestricted_guest_cap(void)
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{
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return !!(msr_read(MSR_IA32_VMX_MISC) & VMX_SUPPORT_UNRESTRICTED_GUEST);
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return ((msr_read(MSR_IA32_VMX_MISC) & VMX_SUPPORT_UNRESTRICTED_GUEST) != 0UL);
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}
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typedef struct _descriptor_table_{
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@ -23,7 +23,7 @@ void get_schedule_lock(uint16_t pcpu_id);
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void release_schedule_lock(uint16_t pcpu_id);
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void set_pcpu_used(uint16_t pcpu_id);
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int allocate_pcpu(void);
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uint16_t allocate_pcpu(void);
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void free_pcpu(uint16_t pcpu_id);
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void add_vcpu_to_runqueue(struct vcpu *vcpu);
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@ -174,13 +174,13 @@ build_bitmap_clear(bitmap_clear, BUS_LOCK, nr, addr)
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*/
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static inline bool bitmap_test(int nr, volatile unsigned long *addr)
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{
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int ret;
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int32_t ret;
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asm volatile("btq %2,%1\n\tsbbl %0, %0"
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: "=r" (ret), "=m" (*addr)
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: "r" ((long)(nr & 0x3f))
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: "cc", "memory");
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return (!!ret);
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return (ret != 0);
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}
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/*
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@ -191,12 +191,12 @@ static inline bool bitmap_test(int nr, volatile unsigned long *addr)
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#define build_bitmap_testandset(name, lock, nr, addr) \
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static inline bool name(int nr, volatile unsigned long *addr) \
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{ \
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int ret; \
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int32_t ret; \
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asm volatile(lock "btsq %2,%1\n\tsbbl %0,%0" \
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: "=r" (ret), "=m" (*addr) \
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: "r" ((long)(nr & 0x3f)) \
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: "cc", "memory"); \
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return (!!ret); \
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return (ret != 0); \
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}
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build_bitmap_testandset(__bitmap_test_and_set, "", nr, addr)
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build_bitmap_testandset(bitmap_test_and_set, BUS_LOCK, nr, addr)
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@ -209,12 +209,12 @@ build_bitmap_testandset(bitmap_test_and_set, BUS_LOCK, nr, addr)
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#define build_bitmap_testandclear(name, lock, nr, addr) \
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static inline bool name(int nr, volatile unsigned long *addr) \
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{ \
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int ret; \
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int32_t ret; \
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asm volatile(lock "btrq %2,%1\n\tsbbl %0,%0" \
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: "=r" (ret), "=m" (*addr) \
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: "r" ((long)(nr & 0x3f)) \
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: "cc", "memory"); \
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return (!!ret); \
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return (ret != 0); \
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}
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build_bitmap_testandclear(__bitmap_test_and_clear, "", nr, addr)
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build_bitmap_testandclear(bitmap_test_and_clear, BUS_LOCK, nr, addr)
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