mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-23 14:07:42 +00:00
HV:misc:add suffix U to the numeric constant
Add suffix U to the numeric constant Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Huihuang Shi
lijinxia
parent
d3ad411c91
commit
96372ed09c
@ -947,8 +947,8 @@ static void get_entry_info(struct ptdev_remapping_info *entry, char *type,
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} else {
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strcpy_s(type, 16, "NONE");
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*irq = IRQ_INVALID;
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*vector = 0;
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*dest = 0;
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*vector = 0U;
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*dest = 0UL;
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*lvl_tm = 0;
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*pin = -1;
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*vpin = -1;
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@ -13,13 +13,13 @@
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#endif
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spinlock_t trampoline_spinlock = {
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.head = 0,
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.tail = 0
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.head = 0U,
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.tail = 0U
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};
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spinlock_t up_count_spinlock = {
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.head = 0,
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.tail = 0
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.head = 0U,
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.tail = 0U
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};
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struct per_cpu_region *per_cpu_data_base_ptr;
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@ -87,7 +87,7 @@ static inline bool get_monitor_cap(void)
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* in hypervisor, but still expose it to the guests and
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* let them handle it correctly
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*/
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if (boot_cpu_data.x86 != 0x6 || boot_cpu_data.x86_model != 0x5c)
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if (boot_cpu_data.x86 != 0x6U || boot_cpu_data.x86_model != 0x5cU)
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return true;
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}
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@ -188,8 +188,8 @@ static int hardware_detect_support(void)
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pr_fatal("%s, LM not supported\n", __func__);
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return -ENODEV;
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}
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if ((boot_cpu_data.x86_phys_bits == 0) ||
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(boot_cpu_data.x86_virt_bits == 0)) {
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if ((boot_cpu_data.x86_phys_bits == 0U) ||
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(boot_cpu_data.x86_virt_bits == 0U)) {
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pr_fatal("%s, can't detect Linear/Physical Address size\n",
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__func__);
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return -ENODEV;
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@ -255,7 +255,7 @@ uint16_t __attribute__((weak)) parse_madt(uint8_t *lapic_id_base)
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static const uint8_t lapic_id[] = {0U, 2U, 4U, 6U};
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uint32_t i;
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for (i = 0; i < ARRAY_SIZE(lapic_id); i++)
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for (i = 0U; i < ARRAY_SIZE(lapic_id); i++)
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*lapic_id_base++ = lapic_id[i];
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return ARRAY_SIZE(lapic_id);
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@ -729,7 +729,7 @@ void start_cpus()
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* configured time-out has expired
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*/
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timeout = CONFIG_CPU_UP_TIMEOUT * 1000;
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while ((up_count != expected_up) && (timeout != 0)) {
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while ((up_count != expected_up) && (timeout != 0U)) {
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/* Delay 10us */
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udelay(10);
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@ -762,7 +762,7 @@ void stop_cpus()
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}
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expected_up = 1;
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while ((up_count != expected_up) && (timeout !=0)) {
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while ((up_count != expected_up) && (timeout != 0U)) {
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/* Delay 10us */
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udelay(10);
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@ -875,11 +875,11 @@ static void vapic_cap_detect(void)
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uint8_t features;
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uint64_t msr_val;
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features = 0;
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features = 0U;
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msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS);
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if (!is_ctrl_setting_allowed(msr_val, VMX_PROCBASED_CTLS_TPR_SHADOW)) {
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cpu_caps.vapic_features = 0;
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cpu_caps.vapic_features = 0U;
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return;
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}
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features |= VAPIC_FEATURE_TPR_SHADOW;
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@ -57,13 +57,13 @@ void free_ept_mem(void *pml4_addr)
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return;
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}
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for (pml4_index = 0; pml4_index < IA32E_NUM_ENTRIES; pml4_index++) {
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for (pml4_index = 0U; pml4_index < IA32E_NUM_ENTRIES; pml4_index++) {
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/* Walk from the PML4 table to the PDPT table */
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pdpt_addr = HPA2HVA(find_next_table(pml4_index, pml4_addr));
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if (pdpt_addr == NULL)
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continue;
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for (pdpt_index = 0; pdpt_index < IA32E_NUM_ENTRIES;
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for (pdpt_index = 0U; pdpt_index < IA32E_NUM_ENTRIES;
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pdpt_index++) {
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/* Walk from the PDPT table to the PD table */
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pde_addr = HPA2HVA(find_next_table(pdpt_index,
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@ -72,7 +72,7 @@ void free_ept_mem(void *pml4_addr)
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if (pde_addr == NULL)
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continue;
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for (pde_index = 0; pde_index < IA32E_NUM_ENTRIES;
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for (pde_index = 0U; pde_index < IA32E_NUM_ENTRIES;
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pde_index++) {
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/* Walk from the PD table to the page table */
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pte_addr = HPA2HVA(find_next_table(pde_index,
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@ -105,7 +105,7 @@ void destroy_ept(struct vm *vm)
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*/
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if (vm->sworld_control.sworld_enabled && (vm->arch_vm.sworld_eptp != 0U)) {
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free_ept_mem(HPA2HVA(vm->arch_vm.sworld_eptp));
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vm->arch_vm.sworld_eptp = 0;
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vm->arch_vm.sworld_eptp = 0UL;
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}
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}
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@ -319,7 +319,7 @@ static int dm_emulate_mmio_pre(struct vcpu *vcpu, uint64_t exit_qual)
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vcpu->req.type = REQ_WP;
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}
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if (vcpu->req.type == 0)
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if (vcpu->req.type == 0U)
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vcpu->req.type = REQ_MMIO;
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vcpu->req.reqs.mmio_request.direction = vcpu->mmio.read_write;
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vcpu->req.reqs.mmio_request.address = (long)vcpu->mmio.paddr;
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@ -349,7 +349,7 @@ int ept_violation_vmexit_handler(struct vcpu *vcpu)
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/* TODO: Need to figure out how to determine value being
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* written
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*/
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mmio->value = 0;
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mmio->value = 0UL;
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} else {
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/* Read operation */
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mmio->read_write = HV_MEM_IO_READ;
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@ -358,7 +358,7 @@ int ept_violation_vmexit_handler(struct vcpu *vcpu)
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/* TODO: Need to determine how sign extension is determined for
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* reads
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*/
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mmio->sign_extend_read = 0;
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mmio->sign_extend_read = 0U;
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}
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/* Get the guest physical address */
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@ -37,13 +37,13 @@ void load_gdtr_and_tr(void)
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tss->ist1 = (uint64_t)get_cpu_var(mc_stack) + CONFIG_STACK_SIZE;
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tss->ist2 = (uint64_t)get_cpu_var(df_stack) + CONFIG_STACK_SIZE;
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tss->ist3 = (uint64_t)get_cpu_var(sf_stack) + CONFIG_STACK_SIZE;
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tss->ist4 = 0L;
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tss->ist4 = 0UL;
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/* tss descriptor */
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set_tss_desc(&gdt->host_gdt_tss_descriptors,
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(void *)tss, sizeof(struct tss_64), TSS_AVAIL);
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gdtr.len = sizeof(struct host_gdt) - 1;
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gdtr.len = sizeof(struct host_gdt) - 1U;
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gdtr.gdt = gdt;
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asm volatile ("lgdt %0" ::"m"(gdtr));
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@ -12,7 +12,7 @@ int dm_emulate_pio_post(struct vcpu *vcpu)
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int cur_context = vcpu->arch_vcpu.cur_context;
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union vhm_request_buffer *req_buf = NULL;
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uint32_t mask =
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0xFFFFFFFFul >> (32 - 8 * vcpu->req.reqs.pio_request.size);
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0xFFFFFFFFUL >> (32 - 8 * vcpu->req.reqs.pio_request.size);
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uint64_t *rax;
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req_buf = (union vhm_request_buffer *)(vcpu->vm->sw.io_shared_page);
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@ -164,7 +164,7 @@ void allow_guest_io_access(struct vm *vm, uint32_t address, uint32_t nbytes)
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uint32_t a;
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b = vm->arch_vm.iobitmap[0];
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for (i = 0; i < nbytes; i++) {
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for (i = 0U; i < nbytes; i++) {
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if ((address & 0x8000U) != 0U)
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b = vm->arch_vm.iobitmap[1];
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a = address & 0x7fffU;
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@ -180,11 +180,11 @@ static void deny_guest_io_access(struct vm *vm, uint32_t address, uint32_t nbyte
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uint32_t a;
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b = vm->arch_vm.iobitmap[0];
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for (i = 0; i < nbytes; i++) {
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for (i = 0U; i < nbytes; i++) {
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if ((address & 0x8000U) != 0U)
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b = vm->arch_vm.iobitmap[1];
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a = address & 0x7fffU;
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b[a >> 5] |= (1 << (a & 0x1fU));
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b[a >> 5U] |= (1U << (a & 0x1fU));
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address++;
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}
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}
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@ -296,13 +296,13 @@ static uint32_t map_mem_region(void *vaddr, void *paddr,
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default:
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/* Set mapping size to 0 - can't map memory in PML4 */
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mapped_size = 0;
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mapped_size = 0U;
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break;
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}
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/* Check to see if mapping should occur */
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if (mapped_size != 0) {
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if (mapped_size != 0U) {
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/* Get current table entry */
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uint64_t entry = MEM_READ64(table_base + table_offset);
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bool prev_entry_present = false;
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@ -415,7 +415,7 @@ static uint32_t map_mem_region(void *vaddr, void *paddr,
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* TODO: add shootdown APs operation if MMU will be
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* modified after AP start in the future.
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*/
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if ((phys_cpu_num != 0) &&
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if ((phys_cpu_num != 0U) &&
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((pcpu_active_bitmap &
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((1UL << phys_cpu_num) - 1))
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!= (1UL << CPU_BOOT_ID))) {
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@ -620,7 +620,7 @@ void init_paging(void)
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attr_uc);
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/* Modify WB attribute for E820_TYPE_RAM */
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for (i = 0, entry = &e820[0];
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for (i = 0U, entry = &e820[0];
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i < e820_entries;
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i++, entry = &e820[i]) {
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if (entry->type == E820_TYPE_RAM) {
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@ -864,10 +864,10 @@ static uint64_t update_page_table_entry(struct map_params *map_params,
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static uint64_t break_page_table(struct map_params *map_params, void *paddr,
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void *vaddr, uint64_t page_size, bool direct)
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{
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uint32_t i = 0;
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uint32_t i = 0U;
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uint64_t pa;
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uint64_t attr = 0x00;
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uint64_t next_page_size = 0x00;
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uint64_t attr = 0x0UL;
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uint64_t next_page_size = 0x0UL;
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void *sub_tab_addr = NULL;
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struct entry_params entry;
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@ -930,7 +930,7 @@ static uint64_t break_page_table(struct map_params *map_params, void *paddr,
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attr |= (entry.entry_val & 0x7fUL);
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}
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/* write all entries and keep original attr*/
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for (i = 0; i < IA32E_NUM_ENTRIES; i++) {
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for (i = 0U; i < IA32E_NUM_ENTRIES; i++) {
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MEM_WRITE64(sub_tab_addr + (i * IA32E_COMM_ENTRY_SIZE),
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(attr | (pa + (i * next_page_size))));
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}
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@ -1033,7 +1033,7 @@ static int modify_paging(struct map_params *map_params, void *paddr,
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*/
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page_size = break_page_table(map_params,
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paddr, vaddr, page_size, direct);
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if (page_size == 0)
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if (page_size == 0UL)
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return -EINVAL;
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}
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} else {
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@ -1043,7 +1043,7 @@ static int modify_paging(struct map_params *map_params, void *paddr,
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/* The function return the memory size that one entry can map */
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adjust_size = update_page_table_entry(map_params, paddr, vaddr,
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page_size, attr, request_type, direct);
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if (adjust_size == 0)
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if (adjust_size == 0UL)
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return -EINVAL;
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vaddr += adjust_size;
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paddr += adjust_size;
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@ -46,7 +46,7 @@ void setup_notification(void)
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char name[32] = {0};
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cpu = get_cpu_id();
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if (cpu > 0)
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if (cpu > 0U)
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return;
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/* support IPI notification, VM0 will register all CPU */
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@ -21,7 +21,7 @@ void init_softirq(void)
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uint16_t pcpu_id;
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for (pcpu_id = 0U; pcpu_id < phys_cpu_num; pcpu_id++) {
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per_cpu(softirq_pending, pcpu_id) = 0;
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per_cpu(softirq_pending, pcpu_id) = 0UL;
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bitmap_set(SOFTIRQ_ATOMIC, &per_cpu(softirq_pending, pcpu_id));
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}
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}
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@ -28,9 +28,9 @@ struct trusty_mem {
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static struct key_info g_key_info = {
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.size_of_this_struct = sizeof(g_key_info),
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.version = 0,
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.platform = 3,
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.num_seeds = 1
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.version = 0U,
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.platform = 3U,
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.num_seeds = 1U
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};
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#define save_segment(seg, SEG_NAME) \
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@ -71,7 +71,7 @@ static void create_secure_world_ept(struct vm *vm, uint64_t gpa_orig,
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}
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if (!vm->sworld_control.sworld_enabled
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|| vm->arch_vm.sworld_eptp != 0) {
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|| vm->arch_vm.sworld_eptp != 0UL) {
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pr_err("Sworld is not enabled or Sworld eptp is not NULL");
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return;
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}
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@ -323,7 +323,7 @@ static bool setup_trusty_info(struct vcpu *vcpu,
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sizeof(mem->first_page.data.key_info.dseed_list));
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/* Derive dvseed from dseed for Trusty */
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key_info = &mem->first_page.data.key_info;
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for (i = 0; i < g_key_info.num_seeds; i++) {
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for (i = 0U; i < g_key_info.num_seeds; i++) {
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if (hkdf_sha256(key_info->dseed_list[i].seed,
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BUP_MKHI_BOOTLOADER_SEED_LEN,
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g_key_info.dseed_list[i].seed,
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@ -364,11 +364,11 @@ static bool init_secure_world_env(struct vcpu *vcpu,
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uint64_t base_hpa,
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uint32_t size)
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{
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vcpu->arch_vcpu.inst_len = 0;
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vcpu->arch_vcpu.inst_len = 0U;
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vcpu->arch_vcpu.contexts[SECURE_WORLD].rip = entry_gpa;
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vcpu->arch_vcpu.contexts[SECURE_WORLD].rsp =
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TRUSTY_EPT_REBASE_GPA + size;
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vcpu->arch_vcpu.contexts[SECURE_WORLD].tsc_offset = 0;
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vcpu->arch_vcpu.contexts[SECURE_WORLD].tsc_offset = 0UL;
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vcpu->arch_vcpu.contexts[SECURE_WORLD].cr0 =
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vcpu->arch_vcpu.contexts[NORMAL_WORLD].cr0;
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@ -412,12 +412,12 @@ bool initialize_trusty(struct vcpu *vcpu, uint64_t param)
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return false;
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}
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if (boot_param->entry_point == 0) {
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if (boot_param->entry_point == 0U) {
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pr_err("%s: Invalid entry point\n", __func__);
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return false;
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}
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if (boot_param->base_addr == 0) {
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if (boot_param->base_addr == 0U) {
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pr_err("%s: Invalid memory base address\n", __func__);
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return false;
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}
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@ -451,7 +451,7 @@ bool initialize_trusty(struct vcpu *vcpu, uint64_t param)
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void trusty_set_dseed(void *dseed, uint8_t dseed_num)
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{
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/* Use fake seed if input param is invalid */
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if ((dseed == NULL) || (dseed_num == 0) ||
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if ((dseed == NULL) || (dseed_num == 0U) ||
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(dseed_num > BOOTLOADER_SEED_MAX_ENTRIES)) {
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g_key_info.num_seeds = 1;
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@ -307,7 +307,7 @@ static int xsetbv_vmexit_handler(struct vcpu *vcpu)
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val64 = exec_vmread(VMX_GUEST_CR4);
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if ((val64 & CR4_OSXSAVE) == 0U) {
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vcpu_inject_gp(vcpu, 0);
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vcpu_inject_gp(vcpu, 0U);
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return -1;
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}
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@ -311,12 +311,12 @@ int vmx_wrmsr_pat(struct vcpu *vcpu, uint64_t value)
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struct run_context *context =
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&vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context];
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for (i = 0; i < 8; i++) {
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field = (value >> (i * 8)) & 0xffU;
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for (i = 0U; i < 8U; i++) {
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field = (value >> (i * 8U)) & 0xffU;
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if ((PAT_MEM_TYPE_INVALID(field) ||
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(PAT_FIELD_RSV_BITS & field) != 0U)) {
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pr_err("invalid guest IA32_PAT: 0x%016llx", value);
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vcpu_inject_gp(vcpu, 0);
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vcpu_inject_gp(vcpu, 0U);
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return -EINVAL;
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}
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}
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@ -364,7 +364,7 @@ int vmx_write_cr0(struct vcpu *vcpu, uint64_t cr0)
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|
||||
if ((cr0 & (cr0_always_off_mask | CR0_RESERVED_MASK)) != 0U) {
|
||||
pr_err("Not allow to set always off / reserved bits for CR0");
|
||||
vcpu_inject_gp(vcpu, 0);
|
||||
vcpu_inject_gp(vcpu, 0U);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -375,7 +375,7 @@ int vmx_write_cr0(struct vcpu *vcpu, uint64_t cr0)
|
||||
!paging_enabled && ((cr0 & CR0_PG) != 0U)) {
|
||||
if ((context->cr4 & CR4_PAE) == 0U) {
|
||||
pr_err("Can't enable long mode when PAE disabled");
|
||||
vcpu_inject_gp(vcpu, 0);
|
||||
vcpu_inject_gp(vcpu, 0U);
|
||||
return -EINVAL;
|
||||
}
|
||||
/* Enable long mode */
|
||||
@ -402,7 +402,7 @@ int vmx_write_cr0(struct vcpu *vcpu, uint64_t cr0)
|
||||
if (((context->cr0 ^ cr0) & (CR0_CD | CR0_NW)) != 0U) {
|
||||
if ((cr0 & CR0_CD) == 0U && ((cr0 & CR0_NW) != 0U)) {
|
||||
pr_err("not allow to set CR0.NW while clearing CR0.CD");
|
||||
vcpu_inject_gp(vcpu, 0);
|
||||
vcpu_inject_gp(vcpu, 0U);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -499,14 +499,14 @@ int vmx_write_cr4(struct vcpu *vcpu, uint64_t cr4)
|
||||
/* Check if guest try to set fixed to 0 bits or reserved bits */
|
||||
if((cr4 & cr4_always_off_mask) != 0U) {
|
||||
pr_err("Not allow to set reserved/always off bits for CR4");
|
||||
vcpu_inject_gp(vcpu, 0);
|
||||
vcpu_inject_gp(vcpu, 0U);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Do NOT support nested guest */
|
||||
if ((cr4 & CR4_VMXE) != 0U) {
|
||||
pr_err("Nested guest not supported");
|
||||
vcpu_inject_gp(vcpu, 0);
|
||||
vcpu_inject_gp(vcpu, 0U);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -601,10 +601,10 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
* if it's resume from S3.
|
||||
*
|
||||
*/
|
||||
if ((uint64_t)vcpu->entry_addr < 0x100000) {
|
||||
sel =((uint64_t)vcpu->entry_addr & 0xFFFF0)
|
||||
>> 4;
|
||||
base = sel << 4;
|
||||
if ((uint64_t)vcpu->entry_addr < 0x100000UL) {
|
||||
sel =((uint64_t)vcpu->entry_addr & 0xFFFF0UL)
|
||||
>> 4UL;
|
||||
base = sel << 4U;
|
||||
} else {
|
||||
/* BSP is initialized with real mode */
|
||||
sel = REAL_MODE_BSP_INIT_CODE_SEL;
|
||||
@ -618,21 +618,21 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
/* AP is initialized with real mode
|
||||
* and CS value is left shift 8 bits from sipi vector;
|
||||
*/
|
||||
sel = vcpu->arch_vcpu.sipi_vector << 8;
|
||||
base = sel << 4;
|
||||
sel = vcpu->arch_vcpu.sipi_vector << 8U;
|
||||
base = sel << 4U;
|
||||
}
|
||||
limit = 0xffff;
|
||||
limit = 0xffffU;
|
||||
access = REAL_MODE_CODE_SEG_AR;
|
||||
} else if (vcpu_mode == CPU_MODE_PROTECTED) {
|
||||
limit = 0xffffffff;
|
||||
base = 0;
|
||||
limit = 0xffffffffU;
|
||||
base = 0U;
|
||||
access = PROTECTED_MODE_CODE_SEG_AR;
|
||||
sel = 0x10; /* Linear CS selector in guest init gdt */
|
||||
sel = 0x10U; /* Linear CS selector in guest init gdt */
|
||||
} else {
|
||||
HV_ARCH_VMX_GET_CS(sel);
|
||||
access = get_cs_access_rights();
|
||||
limit = 0xffffffff;
|
||||
base = 0;
|
||||
limit = 0xffffffffU;
|
||||
base = 0U;
|
||||
}
|
||||
|
||||
/* Selector */
|
||||
@ -660,14 +660,14 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
/***************************************************/
|
||||
/* Set up guest instruction pointer */
|
||||
field = VMX_GUEST_RIP;
|
||||
value32 = 0;
|
||||
value32 = 0U;
|
||||
if (vcpu_mode == CPU_MODE_REAL) {
|
||||
/* RIP is set here */
|
||||
if (is_vcpu_bsp(vcpu)) {
|
||||
if ((uint64_t)vcpu->entry_addr < 0x100000)
|
||||
value32 = (uint64_t)vcpu->entry_addr & 0x0F;
|
||||
if ((uint64_t)vcpu->entry_addr < 0x100000UL)
|
||||
value32 = (uint64_t)vcpu->entry_addr & 0x0FUL;
|
||||
else
|
||||
value32 = 0x0000FFF0;
|
||||
value32 = 0x0000FFF0U;
|
||||
}
|
||||
} else
|
||||
value32 = (uint32_t)((uint64_t)vcpu->entry_addr);
|
||||
@ -678,7 +678,7 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
if (vcpu_mode == CPU_MODE_64BIT) {
|
||||
/* Set up guest stack pointer to 0 */
|
||||
field = VMX_GUEST_RSP;
|
||||
value32 = 0;
|
||||
value32 = 0U;
|
||||
pr_dbg("GUEST RSP on VMEntry %x ",
|
||||
value32);
|
||||
exec_vmwrite(field, value32);
|
||||
@ -691,7 +691,7 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
/* GDTR - Global Descriptor Table */
|
||||
if (vcpu_mode == CPU_MODE_REAL) {
|
||||
/* Base */
|
||||
base = 0;
|
||||
base = 0U;
|
||||
|
||||
/* Limit */
|
||||
limit = 0xFFFF;
|
||||
@ -712,7 +712,7 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
base = gdtb.base;
|
||||
|
||||
/* Limit */
|
||||
limit = HOST_GDT_SIZE - 1;
|
||||
limit = HOST_GDT_SIZE - 1U;
|
||||
}
|
||||
|
||||
/* GDTR Base */
|
||||
@ -729,7 +729,7 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
if ((vcpu_mode == CPU_MODE_REAL) ||
|
||||
(vcpu_mode == CPU_MODE_PROTECTED)) {
|
||||
/* Base */
|
||||
base = 0;
|
||||
base = 0U;
|
||||
|
||||
/* Limit */
|
||||
limit = 0xFFFF;
|
||||
@ -778,14 +778,14 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
} else if (vcpu_mode == CPU_MODE_PROTECTED) {
|
||||
/* Linear data segment in guest init gdt */
|
||||
es = ss = ds = fs = gs = 0x18;
|
||||
limit = 0xffffffff;
|
||||
limit = 0xffffffffU;
|
||||
} else if (vcpu_mode == CPU_MODE_64BIT) {
|
||||
asm volatile ("movw %%es, %%ax":"=a" (es));
|
||||
asm volatile ("movw %%ss, %%ax":"=a" (ss));
|
||||
asm volatile ("movw %%ds, %%ax":"=a" (ds));
|
||||
asm volatile ("movw %%fs, %%ax":"=a" (fs));
|
||||
asm volatile ("movw %%gs, %%ax":"=a" (gs));
|
||||
limit = 0xffffffff;
|
||||
limit = 0xffffffffU;
|
||||
}
|
||||
|
||||
/* Selector */
|
||||
@ -849,7 +849,7 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
pr_dbg("VMX_GUEST_GS_ATTR: 0x%x ", value32);
|
||||
|
||||
/* Base */
|
||||
value = 0;
|
||||
value = 0UL;
|
||||
field = VMX_GUEST_ES_BASE;
|
||||
exec_vmwrite(field, es << 4);
|
||||
pr_dbg("VMX_GUEST_ES_BASE: 0x%016llx ", value);
|
||||
@ -875,17 +875,17 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
pr_dbg("VMX_GUEST_LDTR_SEL: 0x%x ", value32);
|
||||
|
||||
field = VMX_GUEST_LDTR_LIMIT;
|
||||
value32 = 0xffffffff;
|
||||
value32 = 0xffffffffU;
|
||||
exec_vmwrite(field, value32);
|
||||
pr_dbg("VMX_GUEST_LDTR_LIMIT: 0x%x ", value32);
|
||||
|
||||
field = VMX_GUEST_LDTR_ATTR;
|
||||
value32 = 0x10000;
|
||||
value32 = 0x10000U;
|
||||
exec_vmwrite(field, value32);
|
||||
pr_dbg("VMX_GUEST_LDTR_ATTR: 0x%x ", value32);
|
||||
|
||||
field = VMX_GUEST_LDTR_BASE;
|
||||
value32 = 0x00;
|
||||
value32 = 0x00U;
|
||||
exec_vmwrite(field, value32);
|
||||
pr_dbg("VMX_GUEST_LDTR_BASE: 0x%x ", value32);
|
||||
|
||||
@ -896,34 +896,34 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
pr_dbg("VMX_GUEST_TR_SEL: 0x%x ", value32);
|
||||
|
||||
field = VMX_GUEST_TR_LIMIT;
|
||||
value32 = 0xff;
|
||||
value32 = 0xffU;
|
||||
exec_vmwrite(field, value32);
|
||||
pr_dbg("VMX_GUEST_TR_LIMIT: 0x%x ", value32);
|
||||
|
||||
field = VMX_GUEST_TR_ATTR;
|
||||
value32 = 0x8b;
|
||||
value32 = 0x8bU;
|
||||
exec_vmwrite(field, value32);
|
||||
pr_dbg("VMX_GUEST_TR_ATTR: 0x%x ", value32);
|
||||
|
||||
field = VMX_GUEST_TR_BASE;
|
||||
value32 = 0x00;
|
||||
value32 = 0x00U;
|
||||
exec_vmwrite(field, value32);
|
||||
pr_dbg("VMX_GUEST_TR_BASE: 0x%x ", value32);
|
||||
|
||||
field = VMX_GUEST_INTERRUPTIBILITY_INFO;
|
||||
value32 = 0;
|
||||
value32 = 0U;
|
||||
exec_vmwrite(field, value32);
|
||||
pr_dbg("VMX_GUEST_INTERRUPTIBILITY_INFO: 0x%x ",
|
||||
value32);
|
||||
|
||||
field = VMX_GUEST_ACTIVITY_STATE;
|
||||
value32 = 0;
|
||||
value32 = 0U;
|
||||
exec_vmwrite(field, value32);
|
||||
pr_dbg("VMX_GUEST_ACTIVITY_STATE: 0x%x ",
|
||||
value32);
|
||||
|
||||
field = VMX_GUEST_SMBASE;
|
||||
value32 = 0;
|
||||
value32 = 0U;
|
||||
exec_vmwrite(field, value32);
|
||||
pr_dbg("VMX_GUEST_SMBASE: 0x%x ", value32);
|
||||
|
||||
@ -941,14 +941,14 @@ static void init_guest_state(struct vcpu *vcpu)
|
||||
pr_dbg("VMX_GUEST_IA32_PAT: 0x%016llx ",
|
||||
value64);
|
||||
|
||||
value64 = 0;
|
||||
value64 = 0UL;
|
||||
exec_vmwrite64(VMX_GUEST_IA32_DEBUGCTL_FULL, value64);
|
||||
pr_dbg("VMX_GUEST_IA32_DEBUGCTL: 0x%016llx ",
|
||||
value64);
|
||||
|
||||
/* Set up guest pending debug exception */
|
||||
field = VMX_GUEST_PENDING_DEBUG_EXCEPT;
|
||||
value = 0x0;
|
||||
value = 0x0UL;
|
||||
exec_vmwrite(field, value);
|
||||
pr_dbg("VMX_GUEST_PENDING_DEBUG_EXCEPT: 0x%016llx ", value);
|
||||
|
||||
@ -1305,7 +1305,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
|
||||
* on corresponding guest * exception - pg 2902 24.6.3
|
||||
* enable VM exit on MC only
|
||||
*/
|
||||
value32 = (1 << IDT_MC);
|
||||
value32 = (1U << IDT_MC);
|
||||
exec_vmwrite(VMX_EXCEPTION_BITMAP, value32);
|
||||
|
||||
/* Set up page fault error code mask - second paragraph * pg 2902
|
||||
|
||||
@ -180,7 +180,7 @@ static int register_hrhd_units(void)
|
||||
return -1;
|
||||
}
|
||||
|
||||
for (i = 0; i < info->drhd_count; i++) {
|
||||
for (i = 0U; i < info->drhd_count; i++) {
|
||||
drhd_rt = calloc(1, sizeof(struct dmar_drhd_rt));
|
||||
ASSERT(drhd_rt != NULL, "");
|
||||
drhd_rt->drhd = &info->drhd_units[i];
|
||||
@ -235,7 +235,7 @@ static void iommu_flush_cache(struct dmar_drhd_rt *dmar_uint,
|
||||
if (iommu_ecap_c(dmar_uint->ecap) != 0U)
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i += CACHE_LINE_SIZE)
|
||||
for (i = 0U; i < size; i += CACHE_LINE_SIZE)
|
||||
clflush((char *)p + i);
|
||||
}
|
||||
|
||||
@ -339,7 +339,7 @@ dmar_unit_support_aw(struct dmar_drhd_rt *dmar_uint, uint32_t addr_width)
|
||||
|
||||
aw = (uint8_t)width_to_agaw(addr_width);
|
||||
|
||||
return ((1 << aw) & iommu_cap_sagaw(dmar_uint->cap)) != 0;
|
||||
return ((1U << aw) & iommu_cap_sagaw(dmar_uint->cap)) != 0;
|
||||
}
|
||||
|
||||
static void dmar_enable_translation(struct dmar_drhd_rt *dmar_uint)
|
||||
@ -425,8 +425,8 @@ static void dmar_register_hrhd(struct dmar_drhd_rt *dmar_uint)
|
||||
|
||||
dmar_uint->max_domain_id = iommu_cap_ndoms(dmar_uint->cap) - 1;
|
||||
|
||||
if (dmar_uint->max_domain_id > 63)
|
||||
dmar_uint->max_domain_id = 63;
|
||||
if (dmar_uint->max_domain_id > 63U)
|
||||
dmar_uint->max_domain_id = 63U;
|
||||
|
||||
if (max_domain_id > dmar_uint->max_domain_id)
|
||||
max_domain_id = dmar_uint->max_domain_id;
|
||||
@ -456,7 +456,7 @@ static struct dmar_drhd_rt *device_to_dmaru(uint16_t segment, uint8_t bus,
|
||||
if (dmar_uint->drhd->segment != segment)
|
||||
continue;
|
||||
|
||||
for (i = 0; i < dmar_uint->drhd->dev_cnt; i++) {
|
||||
for (i = 0U; i < dmar_uint->drhd->dev_cnt; i++) {
|
||||
if ((dmar_uint->drhd->devices[i].bus == bus) &&
|
||||
(dmar_uint->drhd->devices[i].devfun == devfun))
|
||||
return dmar_uint;
|
||||
@ -481,8 +481,8 @@ static uint8_t alloc_domain_id(void)
|
||||
/* domain id 0 is reserved, when CM = 1.
|
||||
* so domain id allocation start from 1
|
||||
*/
|
||||
for (i = 1; i < 64; i++) {
|
||||
mask = (1 << i);
|
||||
for (i = 1U; i < 64U; i++) {
|
||||
mask = (1UL << i);
|
||||
if ((domain_bitmap & mask) == 0) {
|
||||
domain_bitmap |= mask;
|
||||
break;
|
||||
@ -509,8 +509,8 @@ static struct iommu_domain *create_host_domain(void)
|
||||
domain->is_host = true;
|
||||
domain->dom_id = alloc_domain_id();
|
||||
/* dmar uint need to support translation passthrough */
|
||||
domain->trans_table_ptr = 0;
|
||||
domain->addr_width = 48;
|
||||
domain->trans_table_ptr = 0UL;
|
||||
domain->addr_width = 48U;
|
||||
|
||||
return domain;
|
||||
}
|
||||
@ -846,7 +846,7 @@ struct iommu_domain *create_iommu_domain(int vm_id, uint64_t translation_table,
|
||||
|
||||
/* TODO: check if a domain with the vm_id exists */
|
||||
|
||||
if (translation_table == 0) {
|
||||
if (translation_table == 0UL) {
|
||||
pr_err("translation table is NULL");
|
||||
return NULL;
|
||||
}
|
||||
@ -857,7 +857,7 @@ struct iommu_domain *create_iommu_domain(int vm_id, uint64_t translation_table,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
domain = calloc(1, sizeof(struct iommu_domain));
|
||||
domain = calloc(1U, sizeof(struct iommu_domain));
|
||||
|
||||
ASSERT(domain != NULL, "");
|
||||
domain->is_host = false;
|
||||
@ -910,8 +910,8 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment,
|
||||
uint64_t *context_table;
|
||||
struct dmar_root_entry *root_entry;
|
||||
struct dmar_context_entry *context_entry;
|
||||
uint64_t upper = 0;
|
||||
uint64_t lower = 0;
|
||||
uint64_t upper = 0UL;
|
||||
uint64_t lower = 0UL;
|
||||
|
||||
if (domain == NULL)
|
||||
return 1;
|
||||
@ -935,7 +935,7 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment,
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (dmar_uint->root_table_addr == 0) {
|
||||
if (dmar_uint->root_table_addr == 0UL) {
|
||||
void *root_table_vaddr = alloc_paging_struct();
|
||||
|
||||
if (root_table_vaddr != NULL) {
|
||||
@ -964,7 +964,7 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment,
|
||||
lower = DMAR_SET_BITSLICE(lower,
|
||||
ROOT_ENTRY_LOWER_PRESENT, 1);
|
||||
|
||||
root_entry->upper = 0;
|
||||
root_entry->upper = 0UL;
|
||||
root_entry->lower = lower;
|
||||
iommu_flush_cache(dmar_uint, root_entry,
|
||||
sizeof(struct dmar_root_entry));
|
||||
@ -992,8 +992,8 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment,
|
||||
}
|
||||
|
||||
/* setup context entry for the devfun */
|
||||
upper = 0;
|
||||
lower = 0;
|
||||
upper = 0UL;
|
||||
lower = 0UL;
|
||||
if (domain->is_host) {
|
||||
if (iommu_ecap_pt(dmar_uint->ecap) != 0U) {
|
||||
/* When the Translation-type (T) field indicates
|
||||
@ -1069,8 +1069,8 @@ remove_iommu_device(struct iommu_domain *domain, uint16_t segment,
|
||||
}
|
||||
|
||||
/* clear the present bit first */
|
||||
context_entry->lower = 0;
|
||||
context_entry->upper = 0;
|
||||
context_entry->lower = 0UL;
|
||||
context_entry->upper = 0UL;
|
||||
iommu_flush_cache(dmar_uint, context_entry,
|
||||
sizeof(struct dmar_context_entry));
|
||||
|
||||
@ -1143,7 +1143,7 @@ void suspend_iommu(void)
|
||||
{
|
||||
struct dmar_drhd_rt *dmar_unit;
|
||||
struct list_head *pos;
|
||||
uint32_t i, iommu_idx = 0;
|
||||
uint32_t i, iommu_idx = 0U;
|
||||
|
||||
list_for_each(pos, &dmar_drhd_units) {
|
||||
dmar_unit = list_entry(pos, struct dmar_drhd_rt, list);
|
||||
@ -1157,7 +1157,7 @@ void suspend_iommu(void)
|
||||
dmar_invalid_iotlb_global(dmar_unit);
|
||||
|
||||
/* save IOMMU fault register state */
|
||||
for (i = 0; i < IOMMU_FAULT_REGISTER_STATE_NUM; i++)
|
||||
for (i = 0U; i < IOMMU_FAULT_REGISTER_STATE_NUM; i++)
|
||||
iommu_fault_state[iommu_idx][i] =
|
||||
iommu_read32(dmar_unit, DMAR_FECTL_REG +
|
||||
i * IOMMU_FAULT_REGISTER_STATE_NUM);
|
||||
@ -1178,7 +1178,7 @@ void resume_iommu(void)
|
||||
{
|
||||
struct dmar_drhd_rt *dmar_unit;
|
||||
struct list_head *pos;
|
||||
uint32_t i, iommu_idx = 0;
|
||||
uint32_t i, iommu_idx = 0U;
|
||||
|
||||
/* restore IOMMU fault register state */
|
||||
list_for_each(pos, &dmar_drhd_units) {
|
||||
@ -1196,7 +1196,7 @@ void resume_iommu(void)
|
||||
dmar_invalid_iotlb_global(dmar_unit);
|
||||
|
||||
/* restore IOMMU fault register state */
|
||||
for (i = 0; i < IOMMU_FAULT_REGISTER_STATE_NUM; i++)
|
||||
for (i = 0U; i < IOMMU_FAULT_REGISTER_STATE_NUM; i++)
|
||||
iommu_write32(dmar_unit, DMAR_FECTL_REG +
|
||||
i * IOMMU_FAULT_REGISTER_STATE_NUM,
|
||||
iommu_fault_state[iommu_idx][i]);
|
||||
@ -1228,8 +1228,8 @@ int init_iommu(void)
|
||||
|
||||
host_domain = create_host_domain();
|
||||
|
||||
for (bus = 0; bus <= IOMMU_INIT_BUS_LIMIT; bus++) {
|
||||
for (devfun = 0; devfun <= 255; devfun++) {
|
||||
for (bus = 0U; bus <= IOMMU_INIT_BUS_LIMIT; bus++) {
|
||||
for (devfun = 0U; devfun <= 255U; devfun++) {
|
||||
add_iommu_device(host_domain, 0,
|
||||
(uint8_t)bus, (uint8_t)devfun);
|
||||
}
|
||||
|
||||
@ -117,11 +117,11 @@ biosacpi_search_rsdp(char *base, int length)
|
||||
if (strncmp(rsdp->signature, ACPI_SIG_RSDP,
|
||||
strnlen_s(ACPI_SIG_RSDP, 8)) == 0) {
|
||||
cp = (uint8_t *)rsdp;
|
||||
sum = 0;
|
||||
sum = NULL;
|
||||
for (idx = 0; idx < RSDP_CHECKSUM_LENGTH; idx++)
|
||||
sum += *(cp + idx);
|
||||
|
||||
if (sum != 0)
|
||||
if (sum != NULL)
|
||||
continue;
|
||||
|
||||
return rsdp;
|
||||
|
||||
@ -254,9 +254,9 @@ static void uart16550_read(struct tgt_uart *tgt_uart, void *buffer,
|
||||
uart16550_read_reg(tgt_uart->base_address, RBR_IDX);
|
||||
|
||||
/* Read 1 byte */
|
||||
*bytes_read = 1;
|
||||
*bytes_read = 1U;
|
||||
} else {
|
||||
*bytes_read = 0;
|
||||
*bytes_read = 0U;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user