github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-09-06 19:30:46 +00:00
Code Issues Projects Releases Wiki Activity

config_tools/data: remove descriptions from scenario XML files

Browse Source 
With a schema for scenario XML files, we no longer need to duplicate the
description, configurability and writeablity attributes in each XML
file.

This patch applies the following transformation to all scenario XML files
in order to remove these attributes.

<xsl:stylesheet
    version="1.0"
    xmlns:xsl="http://www.w3.org/1999/XSL/Transform">

  <xsl:template match="@desc" />
  <xsl:template match="@configurable | @multiselect | @readonly" />

  <!-- The identity template -->
  <xsl:template match="@*|node()">
    <xsl:copy>
      <xsl:apply-templates select="@*|node()"/>
    </xsl:copy>
  </xsl:template>

</xsl:stylesheet>

Tracked-On: #5644
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao
2021-02-01 09:42:53 +08:00
committed by wenlingz
parent d0b05b4020
commit 99f8ea64c1
46 changed files with 6185 additions and 6150 deletions
Download Patch File Download Diff File Expand all files Collapse all files

171
misc/config_tools/data/qemu/sdc.xml
View File

@@ -1,145 +1,146 @@
<?xml version="1.0"?>
<acrn-config board="qemu" scenario="sdc">
<hv>
<DEBUG_OPTIONS desc="Debug options for ACRN hypervisor, only valid on debug version">
<RELEASE desc="Release build. 'y' for Release, 'n' for Debug.">n</RELEASE>
<SERIAL_CONSOLE desc="The serial device which is used for hypervisor debug, only valid on Debug version.">/dev/ttyS0</SERIAL_CONSOLE>
<MEM_LOGLEVEL desc="Default loglevel in memory">5</MEM_LOGLEVEL>
<NPK_LOGLEVEL desc="Default loglevel for the hypervisor NPK log">5</NPK_LOGLEVEL>
<CONSOLE_LOGLEVEL desc="Default loglevel on the serial console">3</CONSOLE_LOGLEVEL>
<LOG_DESTINATION desc="Bitmap of consoles where logs are printed.">7</LOG_DESTINATION>
<LOG_BUF_SIZE desc="Capacity of logbuf for each physical cpu.">0x40000</LOG_BUF_SIZE>
<DEBUG_OPTIONS>
<RELEASE>n</RELEASE>
<SERIAL_CONSOLE>/dev/ttyS0</SERIAL_CONSOLE>
<MEM_LOGLEVEL>5</MEM_LOGLEVEL>
<NPK_LOGLEVEL>5</NPK_LOGLEVEL>
<CONSOLE_LOGLEVEL>3</CONSOLE_LOGLEVEL>
<LOG_DESTINATION>7</LOG_DESTINATION>
<LOG_BUF_SIZE>0x40000</LOG_BUF_SIZE>
</DEBUG_OPTIONS>
<FEATURES>
<RELOC desc="Enable hypervisor relocation">y</RELOC>
<SCHEDULER desc="The CPU scheduler to be used by the hypervisor.">SCHED_BVT</SCHEDULER>
<MULTIBOOT2 desc="Support boot ACRN from multiboot2 protocol.">y</MULTIBOOT2>
<RDT desc="Intel RDT (Resource Director Technology).">
<RDT_ENABLED desc="Enable RDT">n</RDT_ENABLED>
<CDP_ENABLED desc="CDP (Code and Data Prioritization). CDP is an extension of CAT.">n</CDP_ENABLED>
<RELOC>y</RELOC>
<SCHEDULER>SCHED_BVT</SCHEDULER>
<MULTIBOOT2>y</MULTIBOOT2>
<RDT>
<RDT_ENABLED>n</RDT_ENABLED>
<CDP_ENABLED>n</CDP_ENABLED>
</RDT>
<HYPERV_ENABLED desc="Enable Hyper-V enlightenment">y</HYPERV_ENABLED>
<IOMMU_ENFORCE_SNP desc="IOMMU enforce snoop behavior of DMA operation.">n</IOMMU_ENFORCE_SNP>
<ACPI_PARSE_ENABLED desc="Enable ACPI runtime parsing.">y</ACPI_PARSE_ENABLED>
<L1D_VMENTRY_ENABLED desc="Enable L1 cache flush before VM entry.">n</L1D_VMENTRY_ENABLED>
<MCE_ON_PSC_DISABLED desc="Force to disable software workaround for Machine Check Error on Page Size Change.">n</MCE_ON_PSC_DISABLED>
<IVSHMEM desc="IVSHMEM configuration">
<IVSHMEM_ENABLED desc="Enable Share Memory between VMs by IVSHMEM.">n</IVSHMEM_ENABLED>
<IVSHMEM_REGION desc="the shared memory region name (starting with hv:/, size (in MB), and IDs of all VMs (separated by a colon) sharing this region, for example hv:/sharename,2,0:2"></IVSHMEM_REGION>
<HYPERV_ENABLED>y</HYPERV_ENABLED>
<IOMMU_ENFORCE_SNP>n</IOMMU_ENFORCE_SNP>
<ACPI_PARSE_ENABLED>y</ACPI_PARSE_ENABLED>
<L1D_VMENTRY_ENABLED>n</L1D_VMENTRY_ENABLED>
<MCE_ON_PSC_DISABLED>n</MCE_ON_PSC_DISABLED>
<IVSHMEM>
<IVSHMEM_ENABLED>n</IVSHMEM_ENABLED>
<IVSHMEM_REGION/>
</IVSHMEM>
</FEATURES>
<MEMORY>
<STACK_SIZE desc="Capacity of one stack, in bytes.">0x2000</STACK_SIZE>
<HV_RAM_SIZE desc="Size of the RAM region used by the hypervisor">0x07800000</HV_RAM_SIZE>
<HV_RAM_START desc="2M-aligned Start physical address of the RAM region used by the hypervisor.">0x11000000</HV_RAM_START>
<LOW_RAM_SIZE desc="Size of the low RAM region">0x00010000</LOW_RAM_SIZE>
<UOS_RAM_SIZE desc="Size of the User OS (UOS) RAM.">0x20000000</UOS_RAM_SIZE>
<SOS_RAM_SIZE desc="Size of the Service OS (SOS) RAM.">0x100000000</SOS_RAM_SIZE>
<PLATFORM_RAM_SIZE desc="Size of the physical platform RAM">0x100000000</PLATFORM_RAM_SIZE>
<STACK_SIZE>0x2000</STACK_SIZE>
<HV_RAM_SIZE>0x07800000</HV_RAM_SIZE>
<HV_RAM_START>0x11000000</HV_RAM_START>
<LOW_RAM_SIZE>0x00010000</LOW_RAM_SIZE>
<UOS_RAM_SIZE>0x20000000</UOS_RAM_SIZE>
<SOS_RAM_SIZE>0x100000000</SOS_RAM_SIZE>
<PLATFORM_RAM_SIZE>0x100000000</PLATFORM_RAM_SIZE>
</MEMORY>
<CAPACITIES desc="Capacity limits for static assigned data struct or maximum supported resouce">
<IOMMU_BUS_NUM desc="Highest PCI bus ID used during IOMMU initialization.">0x100</IOMMU_BUS_NUM>
<MAX_IR_ENTRIES desc="Maximum number of Interrupt Remapping Entries.">256</MAX_IR_ENTRIES>
<MAX_IOAPIC_NUM desc="Maximum number of IO-APICs.">1</MAX_IOAPIC_NUM>
<MAX_PCI_DEV_NUM desc="Maximum number of PCI devices.">96</MAX_PCI_DEV_NUM>
<MAX_IOAPIC_LINES desc="Maximum number of interrupt lines per IOAPIC.">120</MAX_IOAPIC_LINES>
<MAX_PT_IRQ_ENTRIES desc="Maximum number of interrupt source for PT devices.">64</MAX_PT_IRQ_ENTRIES>
<MAX_MSIX_TABLE_NUM desc="Maximum number of MSI-X tables per device. Please leave it blank if not sure.">16</MAX_MSIX_TABLE_NUM>
<MAX_EMULATED_MMIO desc="Maximum number of emulated MMIO regions.">16</MAX_EMULATED_MMIO>
<CAPACITIES>
<IOMMU_BUS_NUM>0x100</IOMMU_BUS_NUM>
<MAX_IR_ENTRIES>256</MAX_IR_ENTRIES>
<MAX_IOAPIC_NUM>1</MAX_IOAPIC_NUM>
<MAX_PCI_DEV_NUM>96</MAX_PCI_DEV_NUM>
<MAX_IOAPIC_LINES>120</MAX_IOAPIC_LINES>
<MAX_PT_IRQ_ENTRIES>64</MAX_PT_IRQ_ENTRIES>
<MAX_MSIX_TABLE_NUM>16</MAX_MSIX_TABLE_NUM>
<MAX_EMULATED_MMIO>16</MAX_EMULATED_MMIO>
</CAPACITIES>
<MISC_CFG>
<GPU_SBDF desc="Segment, Bus, Device, and function of the GPU.">0x00000010</GPU_SBDF>
<GPU_SBDF>0x00000010</GPU_SBDF>
</MISC_CFG>
</hv>
<vm id="0">
<vm_type desc="Specify the VM type" readonly="true">SOS_VM</vm_type>
<name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN SOS VM</name>
<guest_flags desc="Select all applicable flags for the VM" multiselect="true">
<vm_type>SOS_VM</vm_type>
<name>ACRN SOS VM</name>
<guest_flags>
<guest_flag>0</guest_flag>
</guest_flags>
<clos configurable="0" desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
<clos>
<vcpu_clos>0</vcpu_clos>
</clos>
<memory>
<start_hpa configurable="0" desc="The start physical address in host for the VM">0</start_hpa>
<size configurable="0" desc="The memory size in Bytes for the VM">CONFIG_SOS_RAM_SIZE</size>
<start_hpa>0</start_hpa>
<size>CONFIG_SOS_RAM_SIZE</size>
</memory>
<os_config>
<name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">ACRN Service OS</name>
<kern_type desc="Specify the kernel image type so that hypervisor could load it correctly. Currently support KERNEL_BZIMAGE and KERNEL_ZEPHYR.">KERNEL_BZIMAGE</kern_type>
<kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Linux_bzImage</kern_mod>
<ramdisk_mod desc="The tag for ramdisk image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline."></ramdisk_mod>
<bootargs configurable="0" desc="Specify kernel boot arguments">SOS_VM_BOOTARGS</bootargs>
<name>ACRN Service OS</name>
<kern_type>KERNEL_BZIMAGE</kern_type>
<kern_mod>Linux_bzImage</kern_mod>
<ramdisk_mod/>
<bootargs>SOS_VM_BOOTARGS</bootargs>
</os_config>
<legacy_vuart id="0">
<type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
<base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">SOS_COM1_BASE</base>
<irq configurable="0" desc="vCOM1 irq">SOS_COM1_IRQ</irq>
<type>VUART_LEGACY_PIO</type>
<base>SOS_COM1_BASE</base>
<irq>SOS_COM1_IRQ</irq>
</legacy_vuart>
<legacy_vuart id="1">
<type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
<base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
<irq configurable="0" desc="vCOM2 irq">SOS_COM2_IRQ</irq>
<target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
<target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
<type>VUART_LEGACY_PIO</type>
<base>INVALID_COM_BASE</base>
<irq>SOS_COM2_IRQ</irq>
<target_vm_id>1</target_vm_id>
<target_uart_id>1</target_uart_id>
</legacy_vuart>
<console_vuart id="0">
<base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
<base>INVALID_PCI_BASE</base>
</console_vuart>
<communication_vuart id="1">
<base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
<target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
<target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
<base>INVALID_PCI_BASE</base>
<target_vm_id>1</target_vm_id>
<target_uart_id>1</target_uart_id>
</communication_vuart>
<pci_devs configurable="0" desc="pci devices list">
<pci_dev desc="pci device"></pci_dev>
<pci_devs>
<pci_dev/>
</pci_devs>
<board_private>
<rootfs desc="rootfs for Linux kernel">/dev/vda1</rootfs>
<bootargs desc="Specify kernel boot arguments">
<rootfs>/dev/vda1</rootfs>
<bootargs>
earlyprintk=serial,ttyS0,115200n8 rw rootwait console=tty0 consoleblank=0 no_timer_check ignore_loglevel
ignore_loglevel no_timer_check intel_iommu=off tsc=reliable hvlog=2M@0x1FE00000
</bootargs>
</board_private>
</vm>
<vm id="1">
<vm_type desc="Specify the VM type" readonly="true">POST_STD_VM</vm_type>
<guest_flags desc="Select all applicable flags for the VM" multiselect="true">
<vm_type>POST_STD_VM</vm_type>
<guest_flags>
<guest_flag>0</guest_flag>
</guest_flags>
<cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
<cpu_affinity>
<pcpu_id>1</pcpu_id>
</cpu_affinity>
<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
<clos>
<vcpu_clos>0</vcpu_clos>
</clos>
<epc_section configurable="0" desc="epc section">
<base desc="SGX EPC section base, must be page aligned">0</base>
<size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
<epc_section>
<base>0</base>
<size>0</size>
</epc_section>
<legacy_vuart id="0">
<type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
<base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
<irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
<type>VUART_LEGACY_PIO</type>
<base>INVALID_COM_BASE</base>
<irq>COM1_IRQ</irq>
</legacy_vuart>
<legacy_vuart id="1">
<type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
<base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
<irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
<target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
<target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
<type>VUART_LEGACY_PIO</type>
<base>INVALID_COM_BASE</base>
<irq>COM2_IRQ</irq>
<target_vm_id>0</target_vm_id>
<target_uart_id>1</target_uart_id>
</legacy_vuart>
<console_vuart id="0">
<base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
<base>INVALID_PCI_BASE</base>
</console_vuart>
<communication_vuart id="1">
<base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
<target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
<target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
<base>INVALID_PCI_BASE</base>
<target_vm_id>1</target_vm_id>
<target_uart_id>1</target_uart_id>
</communication_vuart>
</vm>
</acrn-config>