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https://github.com/projectacrn/acrn-hypervisor.git
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modularization: reorg the bsp_boot_init & cpu_secondary_init
reorg both init functions, separate the initilization of different components. v2: - separate into 2 patches, 1 for reorg, 1 for pure move. Tracked-On: #1842 Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Xu, Anthony <anthony.xu@intel.com>
This commit is contained in:
Jason Chen CJ
wenlingz
parent
9e917057e9
commit
9a7d32f024
@ -357,50 +357,6 @@ static void get_cpu_name(void)
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boot_cpu_data.model_name[48] = '\0';
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}
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/* NOTE: this function is using temp stack, and after SWITCH_TO(runtime_sp, to)
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* it will switch to runtime stack.
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*/
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void bsp_boot_init(void)
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{
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uint64_t rsp;
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start_tsc = rdtsc();
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/* Clear BSS */
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(void)memset(&ld_bss_start, 0U,
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(size_t)(&ld_bss_end - &ld_bss_start));
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bitmap_set_nolock(BOOT_CPU_ID, &pcpu_active_bitmap);
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/* Get CPU capabilities thru CPUID, including the physical address bit
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* limit which is required for initializing paging.
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*/
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get_cpu_capabilities();
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get_cpu_name();
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load_cpu_state_data();
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/* Initialize the hypervisor paging */
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init_e820();
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init_paging();
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if (!cpu_has_cap(X86_FEATURE_X2APIC)) {
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panic("x2APIC is not present!");
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}
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early_init_lapic();
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init_percpu_lapic_id();
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load_gdtr_and_tr();
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/* Switch to run-time stack */
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rsp = (uint64_t)(&get_cpu_var(stack)[CONFIG_STACK_SIZE - 1]);
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rsp &= ~(CPU_STACK_ALIGN - 1UL);
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SWITCH_TO(rsp, bsp_boot_post);
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}
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static bool check_cpu_security_config(void)
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{
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if (cpu_has_cap(X86_FEATURE_ARCH_CAP)) {
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@ -423,96 +379,229 @@ static bool check_cpu_security_config(void)
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return true;
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}
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static void bsp_boot_post(void)
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/*TODO: move into debug module */
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static void init_debug_pre(void)
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{
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#ifdef STACK_PROTECTOR
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set_fs_base();
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#endif
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cpu_cap_detect();
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cpu_xsave_init();
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/* Set state for this CPU to initializing */
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cpu_set_current_state(BOOT_CPU_ID, PCPU_STATE_INITIALIZING);
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/* Perform any necessary BSP initialization */
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init_bsp();
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/* Initialize console */
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console_init();
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/* Print Hypervisor Banner */
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print_hv_banner();
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/* Make sure rdtsc is enabled */
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check_tsc();
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/* Calibrate TSC Frequency */
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calibrate_tsc();
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/* Enable logging */
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init_logmsg(CONFIG_LOG_DESTINATION);
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}
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pr_acrnlog("HV version %s-%s-%s %s (daily tag:%s) build by %s, start time %lluus",
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HV_FULL_VERSION,
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HV_BUILD_TIME, HV_BUILD_VERSION, HV_BUILD_TYPE,
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HV_DAILY_TAG,
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HV_BUILD_USER, ticks_to_us(start_tsc));
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pr_acrnlog("API version %u.%u",
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HV_API_MAJOR_VERSION, HV_API_MINOR_VERSION);
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pr_acrnlog("Detect processor: %s", boot_cpu_data.model_name);
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pr_dbg("Core %hu is up", BOOT_CPU_ID);
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if (hardware_detect_support() != 0) {
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panic("hardware not support!");
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/*TODO: move into debug module */
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static void init_debug_post(uint16_t pcpu_id)
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{
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if (pcpu_id == BOOT_CPU_ID) {
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/* Initialize the shell */
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shell_init();
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console_setup_timer();
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}
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/* Warn for security feature not ready */
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if (!check_cpu_security_config()) {
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pr_fatal("SECURITY WARNING!!!!!!");
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pr_fatal("Please apply the latest CPU uCode patch!");
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}
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enable_smep();
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/* Initialize the shell */
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shell_init();
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/* Initialize interrupts */
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interrupt_init(BOOT_CPU_ID);
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profiling_setup();
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}
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/*TODO: move into pass-thru module */
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static void init_passthru(void)
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{
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if (init_iommu() != 0) {
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panic("failed to initialize iommu!");
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}
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timer_init();
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profiling_setup();
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setup_notification();
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setup_posted_intr_notification();
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ptdev_init();
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}
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/*TODO: move into guest-vcpu module */
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static void init_guest(void)
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{
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init_scheduler();
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}
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/* Start all secondary cores */
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startup_paddr = prepare_trampoline();
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start_cpus();
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/*TODO: move into guest-vcpu module */
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static void enter_guest_mode(uint16_t pcpu_id)
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{
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exec_vmxon_instr(pcpu_id);
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ASSERT(get_cpu_id() == BOOT_CPU_ID, "");
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console_setup_timer();
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exec_vmxon_instr(BOOT_CPU_ID);
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(void)prepare_vm(BOOT_CPU_ID);
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#ifdef CONFIG_PARTITION_MODE
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(void)prepare_vm(pcpu_id);
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#else
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if (pcpu_id == BOOT_CPU_ID) {
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(void)prepare_vm(pcpu_id);
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}
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#endif
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default_idle();
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/* Control should not come here */
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cpu_dead(BOOT_CPU_ID);
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cpu_dead(pcpu_id);
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}
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void init_cpu_pre(uint16_t pcpu_id)
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{
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if (pcpu_id == BOOT_CPU_ID) {
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start_tsc = rdtsc();
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/* Clear BSS */
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(void)memset(&ld_bss_start, 0U,
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(size_t)(&ld_bss_end - &ld_bss_start));
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/* Get CPU capabilities thru CPUID, including the physical address bit
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* limit which is required for initializing paging.
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*/
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get_cpu_capabilities();
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get_cpu_name();
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load_cpu_state_data();
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/* Initialize the hypervisor paging */
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init_e820();
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init_paging();
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if (!cpu_has_cap(X86_FEATURE_X2APIC)) {
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panic("x2APIC is not present!");
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}
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cpu_cap_detect();
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early_init_lapic();
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init_percpu_lapic_id();
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} else {
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/* Switch this CPU to use the same page tables set-up by the
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* primary/boot CPU
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*/
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enable_paging();
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early_init_lapic();
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pcpu_id = get_cpu_id_from_lapic_id(get_cur_lapic_id());
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}
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bitmap_set_nolock(pcpu_id, &pcpu_active_bitmap);
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/* Set state for this CPU to initializing */
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cpu_set_current_state(pcpu_id, PCPU_STATE_INITIALIZING);
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}
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void init_cpu_post(uint16_t pcpu_id)
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{
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#ifdef STACK_PROTECTOR
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set_fs_base();
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#endif
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load_gdtr_and_tr();
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enable_smep();
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/* Make sure rdtsc is enabled */
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check_tsc();
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cpu_xsave_init();
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if (pcpu_id == BOOT_CPU_ID) {
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/* Print Hypervisor Banner */
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print_hv_banner();
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/* Calibrate TSC Frequency */
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calibrate_tsc();
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pr_acrnlog("HV version %s-%s-%s %s (daily tag:%s) build by %s, start time %lluus",
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HV_FULL_VERSION,
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HV_BUILD_TIME, HV_BUILD_VERSION, HV_BUILD_TYPE,
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HV_DAILY_TAG,
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HV_BUILD_USER, ticks_to_us(start_tsc));
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pr_acrnlog("API version %u.%u",
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HV_API_MAJOR_VERSION, HV_API_MINOR_VERSION);
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pr_acrnlog("Detect processor: %s", boot_cpu_data.model_name);
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pr_dbg("Core %hu is up", BOOT_CPU_ID);
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if (hardware_detect_support() != 0) {
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panic("hardware not support!");
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}
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/* Warn for security feature not ready */
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if (!check_cpu_security_config()) {
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pr_fatal("SECURITY WARNING!!!!!!");
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pr_fatal("Please apply the latest CPU uCode patch!");
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}
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/* Initialize interrupts */
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interrupt_init(BOOT_CPU_ID);
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timer_init();
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setup_notification();
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setup_posted_intr_notification();
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/* Start all secondary cores */
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startup_paddr = prepare_trampoline();
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start_cpus();
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ASSERT(get_cpu_id() == BOOT_CPU_ID, "");
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} else {
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pr_dbg("Core %hu is up", pcpu_id);
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/* Initialize secondary processor interrupts. */
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interrupt_init(pcpu_id);
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timer_init();
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/* Wait for boot processor to signal all secondary cores to continue */
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wait_sync_change(&pcpu_sync, 0UL);
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}
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}
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static void bsp_boot_post(void)
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{
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/* Perform any necessary BSP initialization */
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init_bsp();
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init_debug_pre();
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init_guest();
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init_cpu_post(BOOT_CPU_ID);
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init_debug_post(BOOT_CPU_ID);
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init_passthru();
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enter_guest_mode(BOOT_CPU_ID);
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}
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/* NOTE: this function is using temp stack, and after SWITCH_TO(runtime_sp, to)
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* it will switch to runtime stack.
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*/
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void bsp_boot_init(void)
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{
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uint64_t rsp;
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init_cpu_pre(BOOT_CPU_ID);
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/* Switch to run-time stack */
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rsp = (uint64_t)(&get_cpu_var(stack)[CONFIG_STACK_SIZE - 1]);
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rsp &= ~(CPU_STACK_ALIGN - 1UL);
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SWITCH_TO(rsp, bsp_boot_post);
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}
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static void cpu_secondary_post(void)
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{
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uint16_t pcpu_id;
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/* Release secondary boot spin-lock to allow one of the next CPU(s) to
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* perform this common initialization
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*/
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spinlock_release(&trampoline_spinlock);
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pcpu_id = get_cpu_id();
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init_cpu_post(pcpu_id);
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init_debug_post(pcpu_id);
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enter_guest_mode(pcpu_id);
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}
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/* NOTE: this function is using temp stack, and after SWITCH_TO(runtime_sp, to)
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@ -522,22 +611,7 @@ void cpu_secondary_init(void)
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{
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uint64_t rsp;
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/* Switch this CPU to use the same page tables set-up by the
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* primary/boot CPU
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*/
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enable_paging();
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enable_smep();
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early_init_lapic();
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/* Find the logical ID of this CPU given the LAPIC ID
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* and Set state for this CPU to initializing
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*/
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cpu_set_current_state(get_cpu_id_from_lapic_id(get_cur_lapic_id()),
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PCPU_STATE_INITIALIZING);
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bitmap_set_nolock(get_cpu_id(), &pcpu_active_bitmap);
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init_cpu_pre(INVALID_CPU_ID);
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/* Switch to run-time stack */
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rsp = (uint64_t)(&get_cpu_var(stack)[CONFIG_STACK_SIZE - 1]);
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@ -545,49 +619,6 @@ void cpu_secondary_init(void)
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SWITCH_TO(rsp, cpu_secondary_post);
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}
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static void cpu_secondary_post(void)
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{
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/* Release secondary boot spin-lock to allow one of the next CPU(s) to
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* perform this common initialization
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*/
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spinlock_release(&trampoline_spinlock);
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#ifdef STACK_PROTECTOR
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set_fs_base();
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#endif
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load_gdtr_and_tr();
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/* Make sure rdtsc is enabled */
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check_tsc();
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pr_dbg("Core %hu is up", get_cpu_id());
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cpu_xsave_init();
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/* Initialize secondary processor interrupts. */
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interrupt_init(get_cpu_id());
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timer_init();
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profiling_setup();
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/* Wait for boot processor to signal all secondary cores to continue */
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wait_sync_change(&pcpu_sync, 0UL);
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exec_vmxon_instr(get_cpu_id());
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#ifdef CONFIG_PARTITION_MODE
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(void)prepare_vm(get_cpu_id());
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#endif
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default_idle();
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/* Control will only come here for secondary
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* CPUs not configured for use.
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*/
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cpu_dead(get_cpu_id());
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}
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static uint16_t get_cpu_id_from_lapic_id(uint32_t lapic_id)
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{
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uint16_t i;
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