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doc: editorial tweaks to "Real-Time (RT) Performance Analysis on ACRN"
Editorial tweaks to the "Real-Time (RT) Performance Analysis on ACRN" document, mostly to improve readibility, no technical content change. Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
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.. _rt_performance_tuning:
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.. _rt_performance_tuning:
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Trace and Data Collection for ACRN Real-Time (RT) Performance Tuning
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Real-Time (RT) Performance Analysis on ACRN
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####################################################################
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###########################################
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The document describes the methods to collect trace/data for ACRN RT VM
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The document describes the methods to collect trace/data for ACRN Real-Time VM (RTVM)
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real-time performance analysis. Two parts are included:
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real-time performance analysis. Two parts are included:
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- Method to use trace for the VM exits analysis.
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- Method to trace ``vmexit`` occurences for analysis.
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- Method to collect performance monitoring counts for tuning based on Performance Monitoring Unit, or PMU.
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- Method to collect Performance Monitoring Counters information for tuning based on Performance Monitoring Unit, or PMU.
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VM exits analysis for ACRN RT performance
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``vmexit`` analysis for ACRN RT performance
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*****************************************
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*******************************************
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VM exits in response to certain instructions and events are a key source of
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``vmexit`` are triggered in response to certain instructions and events and are
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performance degradation in virtual machines. During the runtime of a hard
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a key source of performance degradation in virtual machines. During the runtime
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RTVM of ACRN, the following impacts real-time deterministic latency:
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of a hard RTVM of ACRN, the following impacts real-time deterministic latency:
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- CPUID
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- CPUID
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- TSC_Adjust read/write
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- TSC_Adjust read/write
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@ -22,13 +22,13 @@ RTVM of ACRN, the following impacts real-time deterministic latency:
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- APICID/LDR read
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- APICID/LDR read
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- ICR write
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- ICR write
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Generally, we don't want to see any VM exits occur during the critical section of the RT task.
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Generally, we don't want to see any ``vmexit`` occur during the critical section of the RT task.
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The methodology of VM exits analysis is very simple. First, we clearly
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The methodology of ``vmexit`` analysis is very simple. First, we clearly
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identify the **critical section** of the RT task. The critical section is
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identify the **critical section** of the RT task. The critical section is
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the duration of time where we do not want to see any VM exits occur.
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the duration of time where we do not want to see any ``vmexit`` occur.
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Different RT tasks use different critical sections. This document uses
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Different RT tasks use different critical sections. This document uses
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the cyclictest as an example of how to do VM exits analysis.
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the cyclictest benchmark as an example of how to do ``vmexit`` analysis.
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The critical sections
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The critical sections
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=====================
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=====================
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@ -46,32 +46,33 @@ Here is example pseudocode of a cyclictest implementation.
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next += interval
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next += interval
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}
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}
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Time point ``now`` is the actual point at which the cyclictest is wakeuped
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Time point ``now`` is the actual point at which the cyclictest app is woken up
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and scheduled. Time point ``next`` is the expected point at which we want
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and scheduled. Time point ``next`` is the expected point at which we want
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the cyclictest to be awakened and scheduled. Here we can get the latency by
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the cyclictest to be awakened and scheduled. Here we can get the latency by
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``now - next``. We don't want to see VM exits during ``next`` through ``now``. So, define the start point of critical section as ``next`` and end
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``now - next``. We don't want to see any ``vmexit`` in between ``next`` and ``now``.
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point ``now``.
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So, we define the start point of the critical section as ``next`` and the end
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point as ``now``.
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Log and trace data collection
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Log and trace data collection
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=============================
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=============================
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#. Add timestamps (in TSC) at ``next`` and ``now``.
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#. Add timestamps (in TSC) at ``next`` and ``now``.
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#. Capture the log with the above timestamps in the RTVM.
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#. Capture the log with the above timestamps in the RTVM.
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#. Capture the acrntrace log in the service VM at the same time.
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#. Capture the ``acrntrace`` log in the Service VM at the same time.
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Offline analysis
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Offline analysis
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================
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================
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#. Convert the raw trace data to human readable format.
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#. Convert the raw trace data to human readable format.
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#. Merge the logs in the RTVM and the ACRN hypervisor trace based on timestamps (in TSC).
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#. Merge the logs in the RTVM and the ACRN hypervisor trace based on timestamps (in TSC).
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#. Check to see if any VM exit exists within the critical sections. The pattern is as follows:
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#. Check to see if any ``vmexit`` occured within the critical sections. The pattern is as follows:
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.. figure:: images/vm_exits_log.png
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.. figure:: images/vm_exits_log.png
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:align: center
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:align: center
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:name: vm_exits_log
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:name: vm_exits_log
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Performance monitoring counts collecting
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Collecting Performance Monitoring Counters data
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****************************************
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***********************************************
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Enable Performance Monitoring Unit (PMU) support in VM
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Enable Performance Monitoring Unit (PMU) support in VM
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======================================================
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======================================================
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@ -167,10 +168,10 @@ exported by recent versions of the Linux kernel.
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Refer to https://github.com/andikleen/pmu-tools for pmu usage.
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Refer to https://github.com/andikleen/pmu-tools for pmu usage.
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Top-down Micro-architecture Analysis Method (TMAM)
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Top-down Micro-Architecture Analysis Method (TMAM)
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==================================================
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==================================================
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The Top-down Micro-architecture Analysis Method (TMAM), based on Top-Down
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The Top-down Micro-Architecture Analysis Method (TMAM), based on Top-Down
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Characterization methodology, aims to provide an insight into whether you
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Characterization methodology, aims to provide an insight into whether you
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have made wise choices with your algorithms and data structures. See the
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have made wise choices with your algorithms and data structures. See the
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Intel |reg| 64 and IA-32 `Architectures Optimization Reference Manual <http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf>`_,
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Intel |reg| 64 and IA-32 `Architectures Optimization Reference Manual <http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf>`_,
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