diff --git a/hypervisor/arch/x86/lapic.c b/hypervisor/arch/x86/lapic.c
index 272258b52..3213f4a4f 100644
--- a/hypervisor/arch/x86/lapic.c
+++ b/hypervisor/arch/x86/lapic.c
@@ -271,7 +271,6 @@ void send_single_ipi(uint16_t pcpu_id, uint32_t vector)
 
 /**
  * @pre pcpu_id < CONFIG_MAX_PCPU_NUM
- * @pre target pCPU must be in active state
  *
  * @return None
  */
@@ -279,12 +278,13 @@ void send_single_init(uint16_t pcpu_id)
 {
 	union apic_icr icr;
 
-	if (is_pcpu_active(pcpu_id)) {
-		icr.value_32.hi_32 = per_cpu(lapic_id, pcpu_id);
-		icr.value_32.lo_32 = (INTR_LAPIC_ICR_PHYSICAL << 11U) | (INTR_LAPIC_ICR_INIT << 8U);
+	/*
+	 * Intel SDM Vol3 23.8:
+	 *   The INIT signal is blocked whenever a logical processor is in VMX root operation.
+	 *   It is not blocked in VMX nonroot operation. Instead, INITs cause VM exits
+	 */
+	icr.value_32.hi_32 = per_cpu(lapic_id, pcpu_id);
+	icr.value_32.lo_32 = (INTR_LAPIC_ICR_PHYSICAL << 11U) | (INTR_LAPIC_ICR_INIT << 8U);
 
-		msr_write(MSR_IA32_EXT_APIC_ICR, icr.value);
-	} else {
-		ASSERT(false, "pCPU%u not in active", pcpu_id);
-	}
+	msr_write(MSR_IA32_EXT_APIC_ICR, icr.value);
 }
diff --git a/hypervisor/include/arch/x86/lapic.h b/hypervisor/include/arch/x86/lapic.h
index 3b673568f..57e0f1f01 100644
--- a/hypervisor/include/arch/x86/lapic.h
+++ b/hypervisor/include/arch/x86/lapic.h
@@ -128,6 +128,8 @@ void send_single_ipi(uint16_t pcpu_id, uint32_t vector);
  * @brief Send an INIT signal to a single pCPU
  *
  * @param[in] pcpu_id The id of destination physical cpu
+ *
+ * @return None
  */
 void send_single_init(uint16_t pcpu_id);