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hv: change function parameters: pci_pdev_read_cfg and pci_pdev_write_cfg

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In order to allow these functions to be called without an associated
struct pci_pdev (for example, at the time of PCI bus enumeration), these
two functions can not take the struct vdev as input parameter.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Zide Chen 2018-10-08 08:59:10 -07:00 committed by lijinxia
parent 19e1b9675f
commit 9cc1f57f63
4 changed files with 11 additions and 11 deletions
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9
hypervisor/dm/hw/pci.c
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@ -44,14 +44,14 @@ static uint32_t pci_pdev_calc_address(union pci_bdf bdf, uint32_t offset)
return addr; return addr;
} }
uint32_t pci_pdev_read_cfg(struct pci_pdev *pdev, uint32_t offset, uint32_t bytes) uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes)
{ {
uint32_t addr; uint32_t addr;
uint32_t val; uint32_t val;
spinlock_obtain(&pci_device_lock); spinlock_obtain(&pci_device_lock);
addr = pci_pdev_calc_address(pdev->bdf, offset); addr = pci_pdev_calc_address(bdf, offset);
/* Write address to ADDRESS register */ /* Write address to ADDRESS register */
pio_write32(addr, PCI_CONFIG_ADDR); pio_write32(addr, PCI_CONFIG_ADDR);
@ -73,14 +73,13 @@ uint32_t pci_pdev_read_cfg(struct pci_pdev *pdev, uint32_t offset, uint32_t byte
return val; return val;
} }
void pci_pdev_write_cfg(struct pci_pdev *pdev, uint32_t offset, uint32_t bytes, void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val)
uint32_t val)
{ {
uint32_t addr; uint32_t addr;
spinlock_obtain(&pci_device_lock); spinlock_obtain(&pci_device_lock);
addr = pci_pdev_calc_address(pdev->bdf, offset); addr = pci_pdev_calc_address(bdf, offset);
/* Write address to ADDRESS register */ /* Write address to ADDRESS register */
pio_write32(addr, PCI_CONFIG_ADDR); pio_write32(addr, PCI_CONFIG_ADDR);

2
hypervisor/dm/vpci/pci_priv.h
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@ -73,7 +73,5 @@ void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes,
void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, union pci_bdf vbdf, uint32_t offset, void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, union pci_bdf vbdf, uint32_t offset,
uint32_t bytes, uint32_t *val); uint32_t bytes, uint32_t *val);
uint32_t pci_pdev_read_cfg(struct pci_pdev *pdev, uint32_t offset, uint32_t bytes);
void pci_pdev_write_cfg(struct pci_pdev *pdev, uint32_t offset, uint32_t bytes, uint32_t val);
#endif /* PCI_PRIV_H_ */ #endif /* PCI_PRIV_H_ */

8
hypervisor/dm/vpci/pci_pt.c
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@ -77,10 +77,10 @@ static int vdev_pt_init(struct pci_vdev *vdev)
ret = assign_iommu_device(vm->iommu, vdev->pdev.bdf.bits.b, ret = assign_iommu_device(vm->iommu, vdev->pdev.bdf.bits.b,
(uint8_t)(vdev->pdev.bdf.value & 0xFFU)); (uint8_t)(vdev->pdev.bdf.value & 0xFFU));
pci_command = pci_pdev_read_cfg(&vdev->pdev, PCIR_COMMAND, 2U); pci_command = pci_pdev_read_cfg(vdev->pdev.bdf, PCIR_COMMAND, 2U);
/* Disable INTX */ /* Disable INTX */
pci_command |= 0x400U; pci_command |= 0x400U;
pci_pdev_write_cfg(&vdev->pdev, PCIR_COMMAND, 2U, pci_command); pci_pdev_write_cfg(vdev->pdev.bdf, PCIR_COMMAND, 2U, pci_command);
return ret; return ret;
} }
@ -109,7 +109,7 @@ static int vdev_pt_cfgread(struct pci_vdev *vdev, uint32_t offset,
if (pci_bar_access(offset)) { if (pci_bar_access(offset)) {
*val = pci_vdev_read_cfg(vdev, offset, bytes); *val = pci_vdev_read_cfg(vdev, offset, bytes);
} else { } else {
*val = pci_pdev_read_cfg(&vdev->pdev, offset, bytes); *val = pci_pdev_read_cfg(vdev->pdev.bdf, offset, bytes);
} }
return 0; return 0;
@ -188,7 +188,7 @@ static int vdev_pt_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
vdev_pt_cfgwrite_bar(vdev, offset, bytes, val); vdev_pt_cfgwrite_bar(vdev, offset, bytes, val);
} else { } else {
/* Write directly to physical device's config space */ /* Write directly to physical device's config space */
pci_pdev_write_cfg(&vdev->pdev, offset, bytes, val); pci_pdev_write_cfg(vdev->pdev.bdf, offset, bytes, val);
} }
return 0; return 0;

3
hypervisor/include/dm/pci.h
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@ -157,4 +157,7 @@ static inline bool pci_bar_access(uint32_t offset)
} }
} }
uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes);
void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
#endif /* PCI_H_ */ #endif /* PCI_H_ */