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hv: riscv: fix stack allocation in cpu_ctx_save/cpu_ctx_restore

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The RISC-V calling convention defines a full descending stack, where 'sp'
points to the last used stack address. The current implementation of
cpu_ctx_save() subtracts only CPU_REGS_OFFSET_SCRATCH from 'sp', which
allocates 8 bytes too few and may overwrite the caller's stack contents.

Fix this by adjusting CPU_REGS_OFFSET_LAST to include the last slot,
ensuring the full context save/restore area is properly reserved.

Fixes: 6276763cd (hv: riscv: implement cpu_ctx_save and cpu_ctx_restore)

Tracked-On: #8827
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This commit is contained in:
Shiqing Gao
2025-10-13 11:04:04 +08:00
committed by acrnsi-robot
parent 23b9cacbd2
commit 9d95a6adb6
1 changed files with 2 additions and 1 deletions
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3
hypervisor/include/arch/riscv/asm/offset.h
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@@ -56,6 +56,7 @@
#define CPU_REGS_OFFSET_TVAL 0x118
#define CPU_REGS_OFFSET_SCRATCH 0x120
#define CPU_REGS_OFFSET_LAST CPU_REGS_OFFSET_SCRATCH
/* Total context area size (struct cpu_regs). */
#define CPU_REGS_OFFSET_LAST (CPU_REGS_OFFSET_SCRATCH + 8)
#endif /* RISCV_OFFSET_H */