From 9e471d725895e630b801f00ba225ac0bc069ecd0 Mon Sep 17 00:00:00 2001 From: Xiaoguang Wu Date: Sun, 11 Nov 2018 15:47:06 +0800 Subject: [PATCH] DM USB: xHCI: refine the PLC bit emulation logic during S3 According to xHCI 5.4.8, the Port Link State Change (PLC) bit should not be set to 1 during suspend process. This patch is used to fix it. Tracked-On: #1893 Signed-off-by: Xiaoguang Wu Reviewed-by: Liang Yang Acked-by: Yu Wang --- devicemodel/hw/pci/xhci.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/devicemodel/hw/pci/xhci.c b/devicemodel/hw/pci/xhci.c index bcd990cea..90fa795cf 100644 --- a/devicemodel/hw/pci/xhci.c +++ b/devicemodel/hw/pci/xhci.c @@ -1262,8 +1262,15 @@ pci_xhci_portregs_write(struct pci_xhci_vdev *xdev, case 3: /* U3 */ if (oldpls != newpls) { p->portsc &= ~XHCI_PS_PLS_MASK; - p->portsc |= XHCI_PS_PLS_SET(newpls) | - XHCI_PS_PLC; + p->portsc |= XHCI_PS_PLS_SET(newpls); + + /* + * TODO: + * Should check if this is exactly + * consistent with xHCI spec. + */ + if (newpls == 0) + p->portsc |= XHCI_PS_PLC; if (oldpls != 0 && newpls == 0) { pci_xhci_set_evtrb(&evtrb, port,