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hv: reset CAT Capacity Bitmask(CBM) MSRs

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ACRN get messy default values for some CAT CBM MSRs,
  these unexpected default value will result in TCC
  Software SRAM initializes crash.

  This patch resets above error default values before calling
  CRL(cache reserve library) ABI initializaion function.

Tracked-On: #6780
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is contained in:
Yonghua Huang
2021-11-02 04:45:29 +03:00
committed by wenlingz
parent 828edb2067
commit 9e8c1a1508
2 changed files with 37 additions and 0 deletions
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hypervisor/include/arch/x86/asm/cpuid.h
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@@ -142,6 +142,7 @@
#define CPUID_FEATURES 1U
#define CPUID_TLB 2U
#define CPUID_SERIALNUM 3U
#define CPUID_LEAF_CACHE_TOPOLOGY 4U
#define CPUID_EXTEND_FEATURE 7U
#define CPUID_XSAVE_FEATURES 0xDU
#define CPUID_RDT_ALLOCATION 0x10U