From a0a6eb43c41f2284d7b77dda3c5dfd2f21f25fbf Mon Sep 17 00:00:00 2001 From: Binbin Wu Date: Tue, 30 Apr 2019 10:11:09 +0800 Subject: [PATCH] hv: msr: use UL since ia32_misc_enable is 64bit Merge two parts of different definitions for MSR_IA32_MISC_ENABLE fields. - use the prefix "MSR_IA32_" to align with others - Change MSR_IA32_MISC_ENABLE_XD to MSR_IA32_MISC_ENABLE_XD_DISABLE to align the meaning of the filed since it is "XD bit disable" Use UL instead of U as the filed bit mask because MSR_IA32_MISC_ENABLE is 64-bit. Tracked-On: #2834 Signed-off-by: Binbin Wu Acked-by: Eddie Dong --- hypervisor/arch/x86/cpu_caps.c | 4 ++-- hypervisor/include/arch/x86/msr.h | 25 +++++++++++-------------- 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/hypervisor/arch/x86/cpu_caps.c b/hypervisor/arch/x86/cpu_caps.c index 49513af90..821ff257f 100644 --- a/hypervisor/arch/x86/cpu_caps.c +++ b/hypervisor/arch/x86/cpu_caps.c @@ -77,9 +77,9 @@ bool has_monitor_cap(void) static inline bool is_fast_string_erms_supported_and_enabled(void) { bool ret = false; - uint32_t misc_enable = (uint32_t)msr_read(MSR_IA32_MISC_ENABLE); + uint64_t misc_enable = msr_read(MSR_IA32_MISC_ENABLE); - if ((misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) == 0U) { + if ((misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) == 0UL) { pr_fatal("%s, fast string is not enabled\n", __func__); } else { if (!pcpu_has_cap(X86_FEATURE_ERMS)) { diff --git a/hypervisor/include/arch/x86/msr.h b/hypervisor/include/arch/x86/msr.h index d47fcd649..1924b5e3b 100644 --- a/hypervisor/include/arch/x86/msr.h +++ b/hypervisor/include/arch/x86/msr.h @@ -551,7 +551,17 @@ #define PAT_MEM_TYPE_UCM 0x07UL /* uncached minus */ /* MISC_ENABLE bits: architectural */ -#define MSR_IA32_MISC_ENABLE_FAST_STRING (1U << 0U) +#define MSR_IA32_MISC_ENABLE_FAST_STRING (1UL << 0U) +#define MSR_IA32_MISC_ENABLE_TCC (1UL << 3U) +#define MSR_IA32_MISC_ENABLE_PMA (1UL << 7U) +#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1UL << 11U) +#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1UL << 12U) +#define MSR_IA32_MISC_ENABLE_TM2_ENABLE (1UL << 13U) +#define MSR_IA32_MISC_ENABLE_EITS (1UL << 16U) +#define MSR_IA32_MISC_ENABLE_MONITOR_ENA (1UL << 18U) +#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1UL << 22U) +#define MSR_IA32_MISC_ENABLE_xTPR (1UL << 23U) +#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1UL << 34U) #ifndef ASSEMBLER static inline bool pat_mem_type_invalid(uint64_t x) @@ -624,17 +634,4 @@ void update_msr_bitmap_x2apic_passthru(const struct acrn_vcpu *vcpu); /* Flush L1 D-cache */ #define IA32_L1D_FLUSH (1UL << 0U) -/* MSR_IA32_MISC_ENABLE */ -#define MISC_ENABLE_FAST_STRING (1U << 0U) -#define MISC_ENABLE_TCC (1U << 3U) -#define MISC_ENABLE_PMA (1U << 7U) -#define MISC_ENABLE_BTS_UNAVAIL (1U << 11U) -#define MISC_ENABLE_PEBS_UNAVAIL (1U << 12U) -#define MISC_ENABLE_TM2_ENABLE (1U << 13U) -#define MISC_ENABLE_EITS (1U << 16U) -#define MISC_ENABLE_MONITOR_ENA (1U << 18U) -#define MISC_ENABLE_LIMIT_CPUID (1U << 22U) -#define MISC_ENABLE_xTPR (1U << 23U) -#define MISC_ENABLE_XD (1U << 34U) - #endif /* MSR_H */