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pci: mcfg: limit device bus numbers which could access by ECAM

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Per PCI Firmware Specification Revision 3.0, 4.1.2. MCFG Table Description:
Memory Mapped Enhanced Configuration Space Base Address Allocation Structure
assign the Start Bus Number and the End Bus Number which could decoded by the
Host Bridge. We should not access the PCI device which bus number outside of
the range of [Start Bus Number, End Bus Number).
For ACRN,  we should:
1. Don't detect PCI device which bus number outside the range of
[Start Bus Number, End Bus Number) of MCFG ACPI Table.
2. Only trap the ECAM MMIO size: [MMCFG_BASE_ADDRESS, MMCFG_BASE_ADDRESS +
(End Bus Number - Start Bus Number + 1) * 0x100000) for SOS.

Tracked-On: #5233

Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Li Fei1
2020-08-31 14:16:17 +08:00
committed by wenlingz
parent 03036062cd
commit a2fd8c5a9d
9 changed files with 67 additions and 29 deletions
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4
hypervisor/include/dm/vacpi.h
View File

@@ -23,7 +23,9 @@
#define VIRT_XSDT_ADDR 0x7ff00080UL
/* virtual PCI MMCFG address base for pre/post-launched VM. */
#define VIRT_PCI_MMCFG_BASE 0xE0000000UL
#define UOS_VIRT_PCI_MMCFG_BASE 0xE0000000UL
#define UOS_VIRT_PCI_MMCFG_START_BUS 0x0U
#define UOS_VIRT_PCI_MMCFG_END_BUS 0xFFU
void build_vrsdp(struct acrn_vm *vm);

2
hypervisor/include/dm/vpci.h
View File

@@ -155,7 +155,7 @@ union pci_cfg_addr_reg {
struct acrn_vpci {
spinlock_t lock;
union pci_cfg_addr_reg addr;
uint64_t pci_mmcfg_base;
struct pci_mmcfg_region pci_mmcfg;
uint32_t pci_vdev_cnt;
struct pci_vdev pci_vdevs[CONFIG_MAX_PCI_DEV_NUM];
struct hlist_head vdevs_hlist_heads [VDEV_LIST_HASHSIZE];