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hv: Use 64 bits definition for 64 bits MSR_IA32_VMX_EPT_VPID_CAP operation

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MSR_IA32_VMX_EPT_VPID_CAP is 64 bits. Using 32 bits MACROs with it may
cause the bit expression wrong.

Unify the MSR_IA32_VMX_EPT_VPID_CAP operation with 64 bits definition.

Tracked-On: #5923
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shuo A Liu
2021-06-28 16:02:05 +08:00
committed by wenlingz
parent a65e01ae95
commit a431cff94e
6 changed files with 33 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
hypervisor/include/arch/x86/asm/cpu_caps.h
View File

@@ -50,8 +50,7 @@ bool disable_host_monitor_wait(void);
bool is_apl_platform(void);
bool is_apicv_advanced_feature_supported(void);
bool pcpu_has_cap(uint32_t bit);
bool pcpu_has_vmx_ept_cap(uint32_t bit_mask);
bool pcpu_has_vmx_vpid_cap(uint32_t bit_mask);
bool pcpu_has_vmx_ept_vpid_cap(uint64_t bit_mask);
bool is_apl_platform(void);
bool has_core_cap(uint32_t bit_mask);
bool is_ac_enabled(void);

32
hypervisor/include/arch/x86/asm/vmx.h
View File

@@ -341,28 +341,28 @@
#define VMX_PROCBASED_CTLS3_LOADIWKEY (1U<<0U)
/* MSR_IA32_VMX_EPT_VPID_CAP: EPT and VPID capability bits */
#define VMX_EPT_EXECUTE_ONLY (1U << 0U)
#define VMX_EPT_PAGE_WALK_4 (1U << 6U)
#define VMX_EPT_PAGE_WALK_5 (1U << 7U)
#define VMX_EPTP_UC (1U << 8U)
#define VMX_EPTP_WB (1U << 14U)
#define VMX_EPT_2MB_PAGE (1U << 16U)
#define VMX_EPT_1GB_PAGE (1U << 17U)
#define VMX_EPT_INVEPT (1U << 20U)
#define VMX_EPT_AD (1U << 21U)
#define VMX_EPT_INVEPT_SINGLE_CONTEXT (1U << 25U)
#define VMX_EPT_INVEPT_GLOBAL_CONTEXT (1U << 26U)
#define VMX_EPT_EXECUTE_ONLY (1UL << 0U)
#define VMX_EPT_PAGE_WALK_4 (1UL << 6U)
#define VMX_EPT_PAGE_WALK_5 (1UL << 7U)
#define VMX_EPTP_UC (1UL << 8U)
#define VMX_EPTP_WB (1UL << 14U)
#define VMX_EPT_2MB_PAGE (1UL << 16U)
#define VMX_EPT_1GB_PAGE (1UL << 17U)
#define VMX_EPT_INVEPT (1UL << 20U)
#define VMX_EPT_AD (1UL << 21U)
#define VMX_EPT_INVEPT_SINGLE_CONTEXT (1UL << 25U)
#define VMX_EPT_INVEPT_GLOBAL_CONTEXT (1UL << 26U)
#define VMX_VPID_TYPE_INDIVIDUAL_ADDR 0UL
#define VMX_VPID_TYPE_SINGLE_CONTEXT 1UL
#define VMX_VPID_TYPE_ALL_CONTEXT 2UL
#define VMX_VPID_TYPE_SINGLE_NON_GLOBAL 3UL
#define VMX_VPID_INVVPID (1U << 0U) /* (32 - 32) */
#define VMX_VPID_INVVPID_INDIVIDUAL_ADDR (1U << 8U) /* (40 - 32) */
#define VMX_VPID_INVVPID_SINGLE_CONTEXT (1U << 9U) /* (41 - 32) */
#define VMX_VPID_INVVPID_GLOBAL_CONTEXT (1U << 10U) /* (42 - 32) */
#define VMX_VPID_INVVPID_SINGLE_NON_GLOBAL (1U << 11U) /* (43 - 32) */
#define VMX_VPID_INVVPID (1UL << 32U)
#define VMX_VPID_INVVPID_INDIVIDUAL_ADDR (1UL << 40U)
#define VMX_VPID_INVVPID_SINGLE_CONTEXT (1UL << 41U)
#define VMX_VPID_INVVPID_GLOBAL_CONTEXT (1UL << 42U)
#define VMX_VPID_INVVPID_SINGLE_NON_GLOBAL (1UL << 43U)
#define VMX_EPT_MT_EPTE_SHIFT 3U
#define VMX_EPTP_PWL_MASK 0x38UL