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https://github.com/projectacrn/acrn-hypervisor.git
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misc: Add RISC-V board configuration for QEMU virt platform
Add board XML configuration file for RISC-V QEMU virt machine.
Key features:
- Board and firmware information (U-Boot, QEMU virt platform)
- Memory layout from /proc/iomem
- PCI device configuration for virtio devices
- 4-core processor configuration
- Serial console (ttyS0) at 0x10000000
Added comprehensive FIXME documentation explaining:
1. Most information was manually collected rather than auto-extracted
2. Original board inspector relies on x86-specific mechanisms:
- DMI/SMBIOS (dmidecode) vs Device Tree
- ACPI vs Device Tree
- APIC/IOAPIC vs PLIC/CLINT
- BIOS vs OpenSBI/U-Boot
3. Fields needing RISC-V adaptation:
- AVAILABLE_IRQ_INFO: x86 ISA IRQs (0-15) → PLIC range (1-95+)
- apic_id → hart_id
- IOAPIC, DRHD (not applicable)
The VM is started with:
qemu-system-riscv64 \
-machine virt -nographic -m 2048 -smp 4 \
-kernel /usr/lib/u-boot/qemu-riscv64_smode/uboot.elf \
-device virtio-net-device,netdev=eth0 -netdev user,id=eth0 \
-device virtio-rng-pci \
-drive file=<VM_image_file>,format=raw,if=virtio
Tracked-On: #8814
Reviewed-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Signed-off-by: Wei6 Zhang <wei6.zhang@intel.com>
This commit is contained in:
Wei6 Zhang
acrnsi-robot
198
misc/config_tools/data/qemu-riscv/qemu-riscv.xml
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198
misc/config_tools/data/qemu-riscv/qemu-riscv.xml
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@@ -0,0 +1,198 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!--
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FIXME: This board XML configuration file is a preliminary implementation for RISC-V QEMU virt platform.
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Most of the information in this file has been manually collected and filled in, rather than being
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automatically extracted by a RISC-V-aware board inspector tool. This is because:
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1. The original ACRN board inspector is designed for x86 architecture and relies on x86-specific
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mechanisms such as DMI/SMBIOS (dmidecode), ACPI tables, and x86 interrupt controllers (APIC/IOAPIC).
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2. RISC-V systems use different hardware discovery mechanisms:
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- Device Tree instead of ACPI/DMI
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- PLIC/CLINT instead of APIC/IOAPIC for interrupt handling
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- OpenSBI/U-Boot instead of traditional x86 BIOS
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- Hart IDs instead of APIC IDs for CPU identification
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3. Some fields contain x86-specific concepts that need to be replaced with RISC-V equivalents:
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- AVAILABLE_IRQ_INFO: Currently shows x86 ISA IRQs (0-15), should show PLIC IRQ range (1-95+)
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- apic_id: Should be replaced with hart_id for RISC-V processors
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- IOAPIC, DRHD: Not applicable to RISC-V architecture
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TODO: Implement a RISC-V-specific board inspector that can automatically extract:
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- Board/firmware info from Device Tree (/sys/firmware/devicetree/base)
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- CPU information from /proc/cpuinfo (harts, ISA extensions)
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- PLIC interrupt information from Device Tree and /proc/interrupts
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- Memory layout from /proc/iomem and Device Tree
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- PCI device enumeration (when applicable)
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This file serves as a template and reference for RISC-V platform support development.
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-->
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<acrn-config board="riscv_board">
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<BIOS_INFO>
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BIOS Information
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Vendor: U-Boot
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Version: 2025.01-0ubuntu0.24.04.2
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Release Date: 01/01/2025
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BIOS Revision: 25.1
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</BIOS_INFO>
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<BASE_BOARD_INFO>
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Base Board Information
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Manufacturer: riscv-virtio
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Product Name: qemu
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Version: Not Specified
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</BASE_BOARD_INFO>
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<PCI_DEVICE>
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00:01.0 1af4: 1041 Network controller: Virtio network device
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00:02.0 1af4: 1043 Communication controller: Virtio console
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</PCI_DEVICE>
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<PCI_VID_PID>
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00:01.0 0200: 1af4:1041
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00:02.0 0780: 1af4:1043
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</PCI_VID_PID>
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<WAKE_VECTOR_INFO>
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/* Wake vector not applicable for RISC-V */
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</WAKE_VECTOR_INFO>
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<RESET_REGISTER_INFO>
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/* Reset register info for RISC-V */
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</RESET_REGISTER_INFO>
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<PM_INFO>
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/* Power management info for RISC-V */
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</PM_INFO>
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<S3_INFO>
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/* S3 suspend info */
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</S3_INFO>
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<S5_INFO>
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/* S5 power off info */
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</S5_INFO>
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<DRHD_INFO></DRHD_INFO>
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<CPU_BRAND>
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"RISC-V SiFive U74 Processor"
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</CPU_BRAND>
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<CX_INFO>
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/* Cx data is not available */
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</CX_INFO>
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<PX_INFO>
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/* Px data is not available */
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</PX_INFO>
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<MMCFG_BASE_INFO>
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/* PCI mmcfg base of MCFG */
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#define DEFAULT_PCI_MMCFG_BASE 0xb0000000UL
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</MMCFG_BASE_INFO>
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<TPM_INFO>
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/* no TPM device */
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</TPM_INFO>
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<CLOS_INFO>
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</CLOS_INFO>
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<IOMEM_INFO>
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00101000-00101fff : 101000.rtc rtc@101000
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10000000-100000ff : serial
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10008000-10008fff : 10008000.virtio_mmio virtio_mmio@10008000
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10100000-10100017 : fw_cfg_mem
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20000000-21ffffff : 20000000.flash flash@20000000
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22000000-23ffffff : 20000000.flash flash@20000000
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30000000-3fffffff : PCI ECAM
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40000000-7fffffff : pci@30000000
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40000000-40000fff : 0000:00:01.0
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40001000-40001fff : 0000:00:02.0
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80000000-8005ffff : Reserved
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80060000-fdec2fff : System RAM
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ea200000-ea201fff : Reserved
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ea202000-ecb92827 : Kernel image
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ea202000-eaf6f9e1 : Kernel code
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eb800000-ec3fffff : Kernel rodata
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ec600000-eca83bff : Kernel data
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eca84000-ecb92827 : Kernel bss
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ecb92828-ecbfffff : Reserved
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f2327000-f2328fff : Reserved
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f2527000-f6855fff : Reserved
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f9e00000-fddfffff : Reserved
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fdea7000-fdea7fff : Reserved
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fdea9000-fdea9fff : Reserved
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fdeaa000-fdeaafff : Reserved
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fdeb9000-fdebefff : Reserved
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fdec3000-fdec3fff : Reserved
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fdec4000-fdec4fff : System RAM
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fdec5000-fdee6fff : Reserved
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fdee7000-fef2cfff : System RAM
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fdf2d000-fef2cfff : Reserved
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fef2d000-fef2dfff : Reserved
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fef2e000-ff718fff : System RAM
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ff719000-ff71afff : Reserved
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ff71b000-ffffffff : System RAM
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ff803000-ffa08fff : Reserved
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ffa09000-ffd0afff : Reserved
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ffd0b000-ffd0bfff : Reserved
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ffd0c000-ffde3fff : Reserved
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ffde5000-ffde8fff : Reserved
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ffde9000-ffdf5fff : Reserved
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ffdf6000-ffffffff : Reserved
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400000000-7ffffffff : pci@30000000
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400000000-400003fff : 0000:00:01.0
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400000000-400003fff : virtio-pci-modern
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400004000-400007fff : 0000:00:02.0
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400004000-400007fff : virtio-pci-modern
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</IOMEM_INFO>
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<BLOCK_DEVICE_INFO>
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/dev/vda1: TYPE="ext4"
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</BLOCK_DEVICE_INFO>
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<TTYS_INFO>
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seri:/dev/ttyS0 type:mmio base:0x10000000 irq:14
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</TTYS_INFO>
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<AVAILABLE_IRQ_INFO>
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3, 4, 5, 6, 7, 8, 9, 11
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</AVAILABLE_IRQ_INFO>
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<TOTAL_MEM_INFO>
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4038724 kB
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</TOTAL_MEM_INFO>
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<CPU_PROCESSOR_INFO>
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0, 1, 2, 3
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</CPU_PROCESSOR_INFO>
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<MAX_MSIX_TABLE_NUM>
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3
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</MAX_MSIX_TABLE_NUM>
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<processors>
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<!-- Simplified processors section for RISC-V - keeping essential elements for config tools -->
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<thread>
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<cpu_id>0</cpu_id>
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<apic_id>0x0</apic_id>
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<core_type></core_type>
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</thread>
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<thread>
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<cpu_id>1</cpu_id>
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<apic_id>0x1</apic_id>
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<core_type></core_type>
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</thread>
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<thread>
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<cpu_id>2</cpu_id>
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<apic_id>0x2</apic_id>
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<core_type></core_type>
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</thread>
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<thread>
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<cpu_id>3</cpu_id>
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<apic_id>0x3</apic_id>
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<core_type></core_type>
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</thread>
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</processors>
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<caches>
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<!-- Empty caches section for RISC-V -->
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</caches>
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<ioapics>
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<!-- Empty ioapics section for RISC-V -->
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</ioapics>
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<devices>
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<!-- PCI bus definition for RISC-V with memory resources -->
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<bus id="PCI_ROOT" type="pci" address="0x0" description="RISC-V PCI Root Bus">
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<vendor>0x1234</vendor>
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<identifier>0x1111</identifier>
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<class>0x060000</class>
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<!-- Bus number resource -->
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<resource id="res0" type="bus_number" min="0x0" max="0xff" len="0x100"/>
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<!-- IO port resources (minimal for RISC-V) -->
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<resource id="res1" type="io_port" min="0x1000" max="0xffff" len="0xf000"/>
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<!-- Memory resources based on RISC-V memory layout -->
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<resource id="res2" type="memory" min="0x40000000" max="0x7fffffff" len="0x40000000"/>
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<resource id="res3" type="memory" min="0x400000000" max="0x7ffffffff" len="0x400000000"/>
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</bus>
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</devices>
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</acrn-config>
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