mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-08-03 01:06:53 +00:00
HV: vuart: MISRA clean in vuart.c
1. remove multiple return 2. remove goto 3. fix potential NULL pointer dereferencing 4. rename struct fifo to struct vuart_fifo to avoid naming conflicts. Tracked-On: #2987 Signed-off-by: Conghui Chen <conghui.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Conghui Chen
ACRN System Integration
parent
c61db6ffa0
commit
a4b5e39fab
@ -43,14 +43,14 @@ static uint16_t vuart_com_base = CONFIG_COM_BASE;
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#define vuart_lock(vu) spinlock_obtain(&((vu)->lock))
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#define vuart_unlock(vu) spinlock_release(&((vu)->lock))
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static inline void fifo_reset(struct fifo *fifo)
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static inline void fifo_reset(struct vuart_fifo *fifo)
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{
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fifo->rindex = 0U;
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fifo->windex = 0U;
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fifo->num = 0U;
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}
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static inline void fifo_putchar(struct fifo *fifo, char ch)
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static inline void fifo_putchar(struct vuart_fifo *fifo, char ch)
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{
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fifo->buf[fifo->windex] = ch;
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if (fifo->num < fifo->size) {
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@ -62,21 +62,19 @@ static inline void fifo_putchar(struct fifo *fifo, char ch)
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}
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}
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static inline char fifo_getchar(struct fifo *fifo)
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static inline char fifo_getchar(struct vuart_fifo *fifo)
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{
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char c;
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char c = -1;
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if (fifo->num > 0U) {
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c = fifo->buf[fifo->rindex];
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fifo->rindex = (fifo->rindex + 1U) % fifo->size;
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fifo->num--;
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return c;
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} else {
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return -1;
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}
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return c;
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}
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static inline uint32_t fifo_numchars(const struct fifo *fifo)
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static inline uint32_t fifo_numchars(const struct vuart_fifo *fifo)
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{
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return fifo->num;
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}
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@ -117,15 +115,16 @@ static inline void vuart_fifo_init(struct acrn_vuart *vu)
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*/
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static uint8_t vuart_intr_reason(const struct acrn_vuart *vu)
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{
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uint8_t ret = IIR_NOPEND;
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if (((vu->lsr & LSR_OE) != 0U) && ((vu->ier & IER_ELSI) != 0U)) {
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return IIR_RLS;
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ret = IIR_RLS;
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} else if ((fifo_numchars(&vu->rxfifo) > 0U) && ((vu->ier & IER_ERBFI) != 0U)) {
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return IIR_RXTOUT;
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ret = IIR_RXTOUT;
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} else if (vu->thre_int_pending && ((vu->ier & IER_ETBEI) != 0U)) {
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return IIR_TXRDY;
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} else {
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return IIR_NOPEND;
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ret = IIR_TXRDY;
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}
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return ret;
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}
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struct acrn_vuart *find_vuart_by_port(struct acrn_vm *vm, uint16_t offset)
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@ -136,10 +135,10 @@ struct acrn_vuart *find_vuart_by_port(struct acrn_vm *vm, uint16_t offset)
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/* TODO: support pci vuart find */
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for (i = 0; i < MAX_VUART_NUM_PER_VM; i++) {
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vu = &vm->vuart[i];
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if (vu->active == true && vu->port_base == (offset & ~0x7U)) {
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if (vu->active == true && vu->port_base == (offset & ~0x7U)) {
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ret_vu = vu;
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break;
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}
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}
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}
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return ret_vu;
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}
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@ -194,89 +193,82 @@ static bool vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
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uint8_t value_u8 = (uint8_t)value;
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struct acrn_vuart *target_vu = NULL;
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offset -= vu->port_base;
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target_vu = vu->target_vu;
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if ((offset == UART16550_THR) && target_vu) {
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vuart_write_to_target(target_vu, value_u8);
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return true;
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}
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vuart_lock(vu);
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/*
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* Take care of the special case DLAB accesses first
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*/
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if ((vu->lcr & LCR_DLAB) != 0U) {
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if (offset == UART16550_DLL) {
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vu->dll = value_u8;
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goto done;
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}
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if (offset == UART16550_DLM) {
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vu->dlh = value_u8;
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goto done;
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}
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}
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switch (offset) {
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case UART16550_THR:
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fifo_putchar(&vu->txfifo, (char)value_u8);
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vu->thre_int_pending = true;
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break;
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case UART16550_IER:
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/*
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* Apply mask so that bits 4-7 are 0
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* Also enables bits 0-3 only if they're 1
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*/
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vu->ier = value_u8 & 0x0FU;
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break;
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case UART16550_FCR:
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/*
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* The FCR_ENABLE bit must be '1' for the programming
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* of other FCR bits to be effective.
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*/
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if ((value_u8 & FCR_FIFOE) == 0U) {
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vu->fcr = 0U;
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if (vu) {
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offset -= vu->port_base;
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target_vu = vu->target_vu;
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if ((offset == UART16550_THR) && target_vu) {
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vuart_write_to_target(target_vu, value_u8);
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} else {
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if ((value_u8 & FCR_RFR) != 0U) {
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fifo_reset(&vu->rxfifo);
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vuart_lock(vu);
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/*
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* Take care of the special case DLAB accesses first
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*/
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if ((vu->lcr & LCR_DLAB) != 0U && offset == UART16550_DLL) {
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vu->dll = value_u8;
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} else if ((vu->lcr & LCR_DLAB) != 0U && offset == UART16550_DLM) {
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vu->dlh = value_u8;
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} else {
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switch (offset) {
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case UART16550_THR:
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fifo_putchar(&vu->txfifo, (char)value_u8);
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vu->thre_int_pending = true;
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break;
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case UART16550_IER:
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/*
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* Apply mask so that bits 4-7 are 0
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* Also enables bits 0-3 only if they're 1
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*/
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vu->ier = value_u8 & 0x0FU;
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break;
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case UART16550_FCR:
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/*
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* The FCR_ENABLE bit must be '1' for the programming
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* of other FCR bits to be effective.
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*/
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if ((value_u8 & FCR_FIFOE) == 0U) {
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vu->fcr = 0U;
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} else {
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if ((value_u8 & FCR_RFR) != 0U) {
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fifo_reset(&vu->rxfifo);
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}
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vu->fcr = value_u8 & (FCR_FIFOE | FCR_DMA | FCR_RX_MASK);
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}
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break;
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case UART16550_LCR:
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vu->lcr = value_u8;
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break;
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case UART16550_MCR:
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/* ignore modem */
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break;
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case UART16550_LSR:
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/*
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* Line status register is not meant to be written to
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* during normal operation.
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*/
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break;
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case UART16550_MSR:
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/*
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* As far as I can tell MSR is a read-only register.
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*/
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break;
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case UART16550_SCR:
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vu->scr = value_u8;
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break;
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default:
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/*
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* For the offset that is not handled (either a read-only
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* register or an invalid register), ignore the write to it.
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* Gracefully return if prior case clauses have not been met.
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*/
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break;
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}
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}
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vu->fcr = value_u8 & (FCR_FIFOE | FCR_DMA | FCR_RX_MASK);
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vuart_toggle_intr(vu);
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vuart_unlock(vu);
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}
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break;
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case UART16550_LCR:
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vu->lcr = value_u8;
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break;
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case UART16550_MCR:
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/* ignore modem */
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break;
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case UART16550_LSR:
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/*
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* Line status register is not meant to be written to
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* during normal operation.
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*/
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break;
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case UART16550_MSR:
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/*
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* As far as I can tell MSR is a read-only register.
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*/
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break;
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case UART16550_SCR:
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vu->scr = value_u8;
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break;
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default:
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/*
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* For the offset that is not handled (either a read-only
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* register or an invalid register), ignore the write to it.
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* Gracefully return if prior case clauses have not been met.
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*/
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break;
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}
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done:
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vuart_toggle_intr(vu);
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vuart_unlock(vu);
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return true;
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}
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@ -288,76 +280,76 @@ static bool vuart_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t offs
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struct acrn_vuart *vu = find_vuart_by_port(vm, offset);
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struct pio_request *pio_req = &vcpu->req.reqs.pio;
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offset -= vu->port_base;
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vuart_lock(vu);
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/*
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* Take care of the special case DLAB accesses first
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*/
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if ((vu->lcr & LCR_DLAB) != 0U) {
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if (offset == UART16550_DLL) {
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reg = vu->dll;
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goto done;
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}
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if (offset == UART16550_DLM) {
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reg = vu->dlh;
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goto done;
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}
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}
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switch (offset) {
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case UART16550_RBR:
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vu->lsr &= ~LSR_OE;
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reg = (uint8_t)fifo_getchar(&vu->rxfifo);
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break;
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case UART16550_IER:
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reg = vu->ier;
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break;
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case UART16550_IIR:
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iir = ((vu->fcr & FCR_FIFOE) != 0U) ? IIR_FIFO_MASK : 0U;
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intr_reason = vuart_intr_reason(vu);
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if (vu) {
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offset -= vu->port_base;
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vuart_lock(vu);
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/*
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* Deal with side effects of reading the IIR register
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* Take care of the special case DLAB accesses first
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*/
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if (intr_reason == IIR_TXRDY) {
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vu->thre_int_pending = false;
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}
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iir |= intr_reason;
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reg = iir;
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break;
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case UART16550_LCR:
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reg = vu->lcr;
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break;
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case UART16550_MCR:
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reg = vu->mcr;
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break;
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case UART16550_LSR:
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/* Transmitter is always ready for more data */
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vu->lsr |= LSR_TEMT | LSR_THRE;
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/* Check for new receive data */
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if (fifo_numchars(&vu->rxfifo) > 0U) {
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vu->lsr |= LSR_DR;
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if ((vu->lcr & LCR_DLAB) != 0U) {
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if (offset == UART16550_DLL) {
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reg = vu->dll;
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} else if (offset == UART16550_DLM) {
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reg = vu->dlh;
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} else {
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reg = 0U;
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}
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} else {
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vu->lsr &= ~LSR_DR;
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switch (offset) {
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case UART16550_RBR:
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vu->lsr &= ~LSR_OE;
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reg = (uint8_t)fifo_getchar(&vu->rxfifo);
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break;
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case UART16550_IER:
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reg = vu->ier;
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break;
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case UART16550_IIR:
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iir = ((vu->fcr & FCR_FIFOE) != 0U) ? IIR_FIFO_MASK : 0U;
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intr_reason = vuart_intr_reason(vu);
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/*
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* Deal with side effects of reading the IIR register
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*/
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if (intr_reason == IIR_TXRDY) {
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vu->thre_int_pending = false;
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}
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iir |= intr_reason;
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reg = iir;
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break;
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case UART16550_LCR:
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reg = vu->lcr;
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break;
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case UART16550_MCR:
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reg = vu->mcr;
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break;
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case UART16550_LSR:
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/* Transmitter is always ready for more data */
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vu->lsr |= LSR_TEMT | LSR_THRE;
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/* Check for new receive data */
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if (fifo_numchars(&vu->rxfifo) > 0U) {
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vu->lsr |= LSR_DR;
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} else {
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vu->lsr &= ~LSR_DR;
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}
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reg = vu->lsr;
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/* The LSR_OE bit is cleared on LSR read */
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vu->lsr &= ~LSR_OE;
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break;
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case UART16550_MSR:
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/* ignore modem I*/
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reg = 0U;
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break;
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case UART16550_SCR:
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reg = vu->scr;
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break;
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default:
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reg = 0xFFU;
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break;
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}
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}
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reg = vu->lsr;
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/* The LSR_OE bit is cleared on LSR read */
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vu->lsr &= ~LSR_OE;
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break;
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case UART16550_MSR:
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/* ignore modem I*/
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reg = 0U;
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break;
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case UART16550_SCR:
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reg = vu->scr;
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break;
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default:
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reg = 0xFFU;
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break;
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vuart_toggle_intr(vu);
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pio_req->value = (uint32_t)reg;
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vuart_unlock(vu);
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}
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done:
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vuart_toggle_intr(vu);
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pio_req->value = (uint32_t)reg;
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vuart_unlock(vu);
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return true;
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}
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@ -48,7 +48,7 @@
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#define COM3_IRQ 6U
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#define COM4_IRQ 7U
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struct fifo {
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struct vuart_fifo {
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char *buf;
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uint32_t rindex; /* index to read from */
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uint32_t windex; /* index to write to */
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