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hv: ept: set EPT cache attribute to WB for pSRAM

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pSRAM memory should be cachable. However, it's not a RAM or a normal MMIO,
so we can't use the an exist API to do the EPT mapping and set the EPT cache
attribute to WB for it. Now we assume that SOS must assign the PSRAM area as
a whole and as a separate memory region whose base address is PSRAM_BASE_HPA.
If the hpa of the EPT mapping region is equal to PSRAM_BASE_HPA, we think this
EPT mapping is for pSRAM, we change the EPT mapping cache attribute to WB.

And fix a minor bug when SOS trap out to emulate wbinvd when pSRAM is enabled.

Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Qian Wang
2020-10-27 15:16:56 +08:00
committed by wenlingz
parent 46afb946da
commit a557105e71
2 changed files with 12 additions and 1 deletions
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2
hypervisor/arch/x86/guest/vmexit.c
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@@ -384,7 +384,7 @@ static int32_t wbinvd_vmexit_handler(struct acrn_vcpu *vcpu)
struct acrn_vcpu *other;
/* GUEST_FLAG_RT has not set in post-launched RTVM before it has been created */
if ((is_psram_initialized) || (has_rt_vm() == false)) {
if ((!is_psram_initialized) && (has_rt_vm() == false)) {
cache_flush_invalidate_all();
} else {
if (is_rt_vm(vcpu->vm)) {