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hv: cleanup legacy terminologies in RTCM module

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This patch updates below terminologies according
 to the latest TCC Spec:
  PTCT -> RTCT
  PTCM -> RTCM
  pSRAM -> Software SRAM

Tracked-On: #5649
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is contained in:
Yonghua Huang
2021-01-26 21:15:13 +08:00
committed by wenlingz
parent 806f479108
commit a6420e8cfa
13 changed files with 201 additions and 187 deletions
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43
hypervisor/arch/x86/guest/ept.c
View File

@@ -179,38 +179,43 @@ void ept_flush_leaf_page(uint64_t *pge, uint64_t size)
flush_base_hpa = (*pge & (~(size - 1UL)));
flush_end_hpa = flush_base_hpa + size;
/* When pSRAM is not intialized, both psram_area_bottom and psram_area_top is 0,
/* When Software SRAM is not initialized, both software_sram_area_bottom
* and software_sram_area_top is 0,
* so the below if/else will have no use
*/
if (flush_base_hpa < psram_area_bottom) {
/* Only flush [flush_base_hpa, psram_area_bottom) and [psram_area_top, flush_base_hpa),
* ignore [psram_area_bottom, psram_area_top)
if (flush_base_hpa < software_sram_area_bottom) {
/* Only flush [flush_base_hpa, software_sram_area_bottom)
* and [software_sram_area_top, flush_base_hpa),
* ignore [software_sram_area_bottom, software_sram_area_top)
*/
if (flush_end_hpa > psram_area_top) {
/* Only flush [flush_base_hpa, psram_area_bottom) and [psram_area_top, flush_base_hpa),
* ignore [psram_area_bottom, psram_area_top)
if (flush_end_hpa > software_sram_area_top) {
/* Only flush [flush_base_hpa, software_sram_area_bottom)
* and [software_sram_area_top, flush_base_hpa),
* ignore [software_sram_area_bottom, software_sram_area_top)
*/
flush_size = psram_area_bottom - flush_base_hpa;
flush_size = software_sram_area_bottom - flush_base_hpa;
hva = hpa2hva(flush_base_hpa);
stac();
flush_address_space(hva, flush_size);
clac();
flush_size = flush_end_hpa - psram_area_top;
flush_base_hpa = psram_area_top;
} else if (flush_end_hpa > psram_area_bottom) {
/* Only flush [flush_base_hpa, psram_area_bottom) and
* ignore [psram_area_bottom, flush_end_hpa)
flush_size = flush_end_hpa - software_sram_area_top;
flush_base_hpa = software_sram_area_top;
} else if (flush_end_hpa > software_sram_area_bottom) {
/* Only flush [flush_base_hpa, software_sram_area_bottom) and
* ignore [software_sram_area_bottom, flush_end_hpa)
*/
flush_size = psram_area_bottom - flush_base_hpa;
flush_size = software_sram_area_bottom - flush_base_hpa;
}
} else if (flush_base_hpa < psram_area_top) {
if (flush_end_hpa <= psram_area_top) {
} else if (flush_base_hpa < software_sram_area_top) {
if (flush_end_hpa <= software_sram_area_top) {
flush_size = 0UL;
} else {
/* Only flush [psram_area_top, flush_end_hpa) and ignore [flush_base_hpa, psram_area_top) */
flush_base_hpa = psram_area_top;
flush_size = flush_end_hpa - psram_area_top;
/* Only flush [software_sram_area_top, flush_end_hpa)
* and ignore [flush_base_hpa, software_sram_area_top)
*/
flush_base_hpa = software_sram_area_top;
flush_size = flush_end_hpa - software_sram_area_top;
}
}

68
hypervisor/arch/x86/guest/ve820.c
View File

@@ -14,7 +14,7 @@
#define ENTRY_HPA1_LOW_PART1 2U
#define ENTRY_HPA1_LOW_PART2 4U
#define ENTRY_PSRAM 3U
#define ENTRY_SOFTWARE_SRAM 3U
#define ENTRY_HPA1_HI 8U
static struct e820_entry sos_vm_e820[E820_MAX_ENTRIES];
@@ -133,20 +133,20 @@ static const struct e820_entry pre_ve820_template[E820_MAX_ENTRIES] = {
.length = 0x10000UL, /* 64KB */
.type = E820_TYPE_RESERVED
},
/* pSRAM segment splits the lowmem into two parts */
/* Software SRAM segment splits the lowmem into two parts */
{ /* part1 of lowmem of hpa1*/
.baseaddr = MEM_1M, /* 1MB */
.length = PSRAM_BASE_GPA - MEM_1M,
.length = SOFTWARE_SRAM_BASE_GPA - MEM_1M,
.type = E820_TYPE_RAM
},
{ /* pSRAM */
.baseaddr = PSRAM_BASE_GPA,
.length = PSRAM_MAX_SIZE,
{ /* Software SRAM */
.baseaddr = SOFTWARE_SRAM_BASE_GPA,
.length = SOFTWARE_SRAM_MAX_SIZE,
.type = E820_TYPE_RESERVED
},
{ /* part2 of lowmem of hpa1*/
.baseaddr = PSRAM_BASE_GPA + PSRAM_MAX_SIZE,
.length = MEM_2G - MEM_1M - (PSRAM_BASE_GPA + PSRAM_MAX_SIZE),
.baseaddr = SOFTWARE_SRAM_BASE_GPA + SOFTWARE_SRAM_MAX_SIZE,
.length = MEM_2G - MEM_1M - (SOFTWARE_SRAM_BASE_GPA + SOFTWARE_SRAM_MAX_SIZE),
.type = E820_TYPE_RAM
},
{ /* ACPI Reclaim */
@@ -182,28 +182,33 @@ static inline uint64_t add_ram_entry(struct e820_entry *entry, uint64_t gpa, uin
*
* ve820 layout for pre-launched VM:
*
* entry0: usable under 1MB
* entry1: reserved for MP Table/ACPI RSDP from 0xf0000 to 0xfffff
* entry2: usable, the part1 of hpa1 in lowmem, from 0x100000, and up to the bottom of pSRAM area.
* entry3: reserved, pSRAM segment, which will be identically mapped to physical pSRAM segment rather than hpa1.
* entry4: usable, the part2 of hpa1 in lowmem, from the ceil of pSRAM segment, and up to 2G-1M.
* entry5: ACPI Reclaim from 0x7ff00000 to 0x7ffeffff
* entry6: ACPI NVS from 0x7fff0000 to 0x7fffffff
* entry7: reserved for 32bit PCI hole from 0x80000000 to 0xffffffff
* (entry8): usable for
* a) hpa1_hi, if hpa1 > 2GB - PSRAM_MAX_SIZE
* b) hpa2, if (hpa1 + hpa2) < 2GB - PSRAM_MAX_SIZE
* c) hpa2_lo, if hpa1 < 2GB - PSRAM_MAX_SIZE and (hpa1 + hpa2) > 2GB - PSRAM_MAX_SIZE
* (entry9): usable for
* a) hpa2, if hpa1 > 2GB - PSRAM_MAX_SIZE
* b) hpa2_hi, if hpa1 < 2GB - PSRAM_MAX_SIZE and (hpa1 + hpa2) > 2GB - PSRAM_MAX_SIZE
* entry0: usable under 1MB
* entry1: reserved for MP Table/ACPI RSDP from 0xf0000 to 0xfffff
* entry2: usable, the part1 of hpa1 in lowmem, from 0x100000,
* and up to the bottom of Software SRAM area.
* entry3: reserved, Software SRAM segment, which will be identically mapped to physical
* Software SRAM segment rather than hpa1.
* entry4: usable, the part2 of hpa1 in lowmem, from the ceil of Software SRAM segment,
* and up to 2G-1M.
* entry5: ACPI Reclaim from 0x7ff00000 to 0x7ffeffff
* entry6: ACPI NVS from 0x7fff0000 to 0x7fffffff
* entry7: reserved for 32bit PCI hole from 0x80000000 to 0xffffffff
* (entry8): usable for
* a) hpa1_hi, if hpa1 > 2GB - SOFTWARE_SRAM_MAX_SIZE
* b) hpa2, if (hpa1 + hpa2) < 2GB - SOFTWARE_SRAM_MAX_SIZE
* c) hpa2_lo,
* if hpa1 < 2GB - SOFTWARE_SRAM_MAX_SIZE and (hpa1 + hpa2) > 2GB - SOFTWARE_SRAM_MAX_SIZE
* (entry9): usable for
* a) hpa2, if hpa1 > 2GB - SOFTWARE_SRAM_MAX_SIZE
* b) hpa2_hi,
* if hpa1 < 2GB - SOFTWARE_SRAM_MAX_SIZE and (hpa1 + hpa2) > 2GB - SOFTWARE_SRAM_MAX_SIZE
*/
/*
The actual memory mapping under 2G looks like below:
|<--1M-->|
|<-----hpa1_low_part1--->|
|<---pSRAM--->|
|<---Software SRAM--->|
|<-----hpa1_low_part2--->|
|<---Non-mapped hole (if there is)-->|
|<---1M ACPI NVS/DATA--->|
@@ -213,8 +218,8 @@ void create_prelaunched_vm_e820(struct acrn_vm *vm)
struct acrn_vm_config *vm_config = get_vm_config(vm->vm_id);
uint64_t gpa_start = 0x100000000UL;
uint64_t hpa1_hi_size, hpa2_lo_size;
uint64_t lowmem_max_length = MEM_2G - PSRAM_MAX_SIZE;
uint64_t hpa1_part1_max_length = PSRAM_BASE_GPA - MEM_1M;
uint64_t lowmem_max_length = MEM_2G - SOFTWARE_SRAM_MAX_SIZE;
uint64_t hpa1_part1_max_length = SOFTWARE_SRAM_BASE_GPA - MEM_1M;
uint64_t remaining_hpa2_size = vm_config->memory.size_hpa2;
uint32_t entry_idx = ENTRY_HPA1_HI;
@@ -229,12 +234,17 @@ void create_prelaunched_vm_e820(struct acrn_vm *vm)
gpa_start = add_ram_entry((vm->e820_entries + entry_idx), gpa_start, hpa1_hi_size);
entry_idx++;
} else if (vm_config->memory.size <= MEM_1M + hpa1_part1_max_length + MEM_1M) {
/* in this case, hpa1 is only enough for the first 1M + part1 + last 1M (ACPI NVS/DATA), so part2 will be empty */
vm->e820_entries[ENTRY_HPA1_LOW_PART1].length = vm_config->memory.size - MEM_2M; /* 2M includes the first and last 1M */
/*
* In this case, hpa1 is only enough for the first
* 1M + part1 + last 1M (ACPI NVS/DATA), so part2 will be empty.
* Below 'MEM_2M' includes the first and last 1M
*/
vm->e820_entries[ENTRY_HPA1_LOW_PART1].length = vm_config->memory.size - MEM_2M;
vm->e820_entries[ENTRY_HPA1_LOW_PART2].length = 0;
} else {
/* Otherwise, part2 is not empty. */
vm->e820_entries[ENTRY_HPA1_LOW_PART2].length = vm_config->memory.size - PSRAM_BASE_GPA - MEM_1M;
vm->e820_entries[ENTRY_HPA1_LOW_PART2].length =
vm_config->memory.size - SOFTWARE_SRAM_BASE_GPA - MEM_1M;
/* need to set gpa_start for hpa2 */
}

12
hypervisor/arch/x86/guest/vm.c
View File

@@ -231,12 +231,12 @@ static void prepare_prelaunched_vm_memmap(struct acrn_vm *vm, const struct acrn_
if (entry->length == 0UL) {
continue;
} else {
if (is_psram_initialized && (entry->baseaddr == PSRAM_BASE_GPA) &&
if (is_sw_sram_initialized && (entry->baseaddr == SOFTWARE_SRAM_BASE_GPA) &&
((vm_config->guest_flags & GUEST_FLAG_RT) != 0U)){
/* pass through pSRAM to pre-RTVM */
pr_fatal("%s, %d___", __func__, __LINE__);
/* pass through Software SRAM to pre-RTVM */
ept_add_mr(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
PSRAM_BASE_HPA, PSRAM_BASE_GPA, PSRAM_MAX_SIZE, EPT_RWX | EPT_WB);
SOFTWARE_SRAM_BASE_HPA, SOFTWARE_SRAM_BASE_GPA,
SOFTWARE_SRAM_MAX_SIZE, EPT_RWX | EPT_WB);
continue;
}
}
@@ -365,8 +365,8 @@ static void prepare_sos_vm_memmap(struct acrn_vm *vm)
pci_mmcfg = get_mmcfg_region();
ept_del_mr(vm, (uint64_t *)vm->arch_vm.nworld_eptp, pci_mmcfg->address, get_pci_mmcfg_size(pci_mmcfg));
/* TODO: remove pSRAM from SOS prevent SOS to use clflush to flush the pSRAM cache.
* If we remove this EPT mapping from the SOS, the ACRN-DM can't do pSRAM EPT mapping
/* TODO: remove Software SRAM from SOS prevent SOS to use clflush to flush the Software SRAM cache.
* If we remove this EPT mapping from the SOS, the ACRN-DM can't do Software SRAM EPT mapping
* because the SOS can't get the HPA of this memory region.
*/
}

2
hypervisor/arch/x86/guest/vmexit.c
View File

@@ -404,7 +404,7 @@ static int32_t wbinvd_vmexit_handler(struct acrn_vcpu *vcpu)
struct acrn_vcpu *other;
/* GUEST_FLAG_RT has not set in post-launched RTVM before it has been created */
if ((!is_psram_initialized) && (!has_rt_vm())) {
if ((!is_sw_sram_initialized) && (!has_rt_vm())) {
cache_flush_invalidate_all();
} else {
if (is_rt_vm(vcpu->vm)) {