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hv: remove hardcoding of SW SRAM HPA base

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Physical address to SW SRAM region maybe different
 on different platforms, this hardcoded address may
 result in address mismatch for SW SRAM operations.

 This patch removes above hardcoded address and uses
 the physical address parsed from native RTCT.

Tracked-On: #5649
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Yonghua Huang
2021-01-26 22:56:07 +08:00
committed by wenlingz
parent a6420e8cfa
commit a6e666dbe7
5 changed files with 56 additions and 45 deletions
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7
hypervisor/include/arch/x86/rtct.h
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@@ -20,7 +20,6 @@
#define RTCT_ENTRY_TYPE_RT_IOMMU 8U
#define RTCT_ENTRY_TYPE_MEM_HIERARCHY_LATENCY 9U
#define SOFTWARE_SRAM_BASE_HPA 0x40080000U
#define SOFTWARE_SRAM_BASE_GPA 0x40080000U
#define SOFTWARE_SRAM_MAX_SIZE 0x00800000U
@@ -46,8 +45,6 @@ struct rtct_entry_data_software_sram
uint32_t apic_id_0; /*only the first core is responsible for initialization of L3 mem region*/
} __packed;
extern uint64_t software_sram_area_bottom;
extern uint64_t software_sram_area_top;
uint64_t get_software_sram_base(void);
uint64_t get_software_sram_size(void);
#endif /* RTCT_H */