github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-11-14 10:31:59 +00:00
Code Issues Projects Releases Wiki Activity

[FIXME] hv: risc-v add denpended implementation in cpu.h

Browse Source 
spinlock invokes CPU_INT_ALL_DISABLE & CPU_INT_ALL_RESTOE, bitops
invokes BITS_PER_LONG, add them to pass the build.

current implementation is macro, same as X86. later official mult-arch
change should refactor to static inline on both x86 and risc-v.

Tracked-On: #8803
Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com>
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Reviewed-by: Yifan Liu  <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This commit is contained in:
Haicheng Li
2025-09-15 15:12:42 +08:00
committed by acrnsi-robot
parent 3a74e62ec4
commit a7239d1268
1 changed files with 29 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
hypervisor/include/arch/riscv/asm/cpu.h
View File

@@ -17,6 +17,12 @@
#define cpu_relax() barrier() /* TODO: replace with yield instruction */ #define cpu_relax() barrier() /* TODO: replace with yield instruction */
#define NR_CPUS MAX_PCPU_NUM #define NR_CPUS MAX_PCPU_NUM
#define LONG_BYTEORDER 3
#define BYTES_PER_LONG (1 << LONG_BYTEORDER)
#define BITS_PER_LONG (BYTES_PER_LONG << 3)
/* Define the interrupt enable bit mask */
#define SSTATUS_SIE 0x2
static inline uint16_t get_pcpu_id(void) static inline uint16_t get_pcpu_id(void)
{ {
/** /**
@@ -28,11 +34,28 @@ static inline uint16_t get_pcpu_id(void)
/* Write CSR */ /* Write CSR */
#define cpu_csr_write(reg, csr_val) \ #define cpu_csr_write(reg, csr_val) \
({ \ ({ \
uint64_t val = (uint64_t)csr_val; \ uint64_t val = (uint64_t)csr_val; \
asm volatile (" csrw " STRINGIFY(reg) ", %0 \n\t" \ asm volatile(" csrw " STRINGIFY(reg) ", %0 \n\t" ::"r"(val) : "memory"); \
:: "r"(val): "memory"); \ })
})
/**
* FIXME: to follow multi-arch design, refactor all of them into static inline functions with corresponding
* X86 implementation together.
*/
#define local_irq_disable() asm volatile("csrc sstatus, %0\n" ::"i"(SSTATUS_SIE) : "memory")
#define local_irq_enable() asm volatile("csrs sstatus, %0\n" ::"i"(SSTATUS_SIE) : "memory")
#define local_save_flags(x) ({ asm volatile("csrr %0, sstatus, 0\n" : "=r"(x)::"memory"); })
#define local_irq_restore(x) ({ asm volatile("csrs sstatus, %0\n" ::"rK"(x & SSTATUS_SIE) : "memory"); })
#define local_irq_save(x) \
({ \
uint32_t val = 0U; \
asm volatile("csrrc %0, sstatus, 0\n" : "=r"(val) : "i"(SSTATUS_SIE) : "memory"); \
*(uint32_t *)(x) = val; \
})
#define CPU_INT_ALL_DISABLE(x) local_irq_save(x)
#define CPU_INT_ALL_RESTORE(x) local_irq_restore(x)
void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync); void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync);