diff --git a/hypervisor/Makefile b/hypervisor/Makefile index 318355fff..890245b8f 100644 --- a/hypervisor/Makefile +++ b/hypervisor/Makefile @@ -206,7 +206,6 @@ endif # platform boot component BOOT_S_SRCS += arch/x86/boot/cpu_primary.S -BOOT_S_SRCS += arch/x86/boot/cpu_save_boot_ctx.S BOOT_S_SRCS += arch/x86/boot/trampoline.S BOOT_C_SRCS += boot/multiboot.c ifeq ($(CONFIG_MULTIBOOT2),y) diff --git a/hypervisor/arch/x86/boot/cpu_primary.S b/hypervisor/arch/x86/boot/cpu_primary.S index 1e1950747..8b59986e9 100644 --- a/hypervisor/arch/x86/boot/cpu_primary.S +++ b/hypervisor/arch/x86/boot/cpu_primary.S @@ -160,7 +160,7 @@ cpu_primary_start_32: test $0x400, %eax /* jump to 64bit entry if it is already in long mode */ - jne cpu_primary_start_64 + jne primary_start_long_mode /* Disable paging */ mov %cr0, %ebx @@ -219,23 +219,7 @@ jmpbuf_32: /* 0x0008 = HOST_GDT_RING0_CODE_SEL */ .word 0x0008 - /* - * Offset from the beginning of the entry section. - * This is to make sure that cpu_primary_start_64 is linked to a known address - * so that efi-stub knows where to pass control to hypervisor. - */ - .org 0x200 - .code64 - .global cpu_primary_start_64 -cpu_primary_start_64: - /* save the MULTBOOT magic number & MBI */ - lea boot_regs(%rip), %rax - movl %edi, (%rax) - movl %esi, 4(%rax) - - /* Save boot context from 64bit mode */ - call cpu_primary_save_64 - +.code64 primary_start_long_mode: /* Initialize temporary stack pointer, size = 0x1000 */ diff --git a/hypervisor/arch/x86/boot/cpu_save_boot_ctx.S b/hypervisor/arch/x86/boot/cpu_save_boot_ctx.S deleted file mode 100644 index 4f117ee78..000000000 --- a/hypervisor/arch/x86/boot/cpu_save_boot_ctx.S +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2018 Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - - .section entry, "ax" - .align 8 - - .code64 - .global cpu_primary_save_64 -cpu_primary_save_64: - /* save context from 64bit mode */ - lea boot_context(%rip), %r8 - sgdt BOOT_CTX_GDT_OFFSET(%r8) - sidt BOOT_CTX_IDT_OFFSET(%r8) - str BOOT_CTX_TR_SEL_OFFSET(%r8) - sldt BOOT_CTX_LDT_SEL_OFFSET(%r8) - mov %cr0, %rcx - mov %rcx, BOOT_CTX_CR0_OFFSET(%r8) - mov %cr3, %rcx - mov %rcx, BOOT_CTX_CR3_OFFSET(%r8) - mov %cr4, %rcx - mov %rcx, BOOT_CTX_CR4_OFFSET(%r8) - mov %cs, %cx - mov %cx, BOOT_CTX_CS_SEL_OFFSET(%r8) - lar %ecx, %ecx - /* CS AR start from bit 8 */ - shr $8, %ecx - /* Clear Limit field, bit 8-11 */ - andl $0x0000f0ff, %ecx - mov %ecx, BOOT_CTX_CS_AR_OFFSET(%r8) - - /* Save CS limit field */ - mov %cs, %cx - xor %edx, %edx - lsl %ecx, %edx - mov %edx, BOOT_CTX_CS_LIMIT_OFFSET(%r8) - - mov %es, BOOT_CTX_ES_SEL_OFFSET(%r8) - mov %ss, BOOT_CTX_SS_SEL_OFFSET(%r8) - mov %ds, BOOT_CTX_DS_SEL_OFFSET(%r8) - mov %fs, BOOT_CTX_FS_SEL_OFFSET(%r8) - mov %gs, BOOT_CTX_GS_SEL_OFFSET(%r8) - /* 0xc0000080 = MSR_IA32_EFER */ - movl $0xc0000080, %ecx - rdmsr - movl %eax, BOOT_CTX_EFER_LOW_OFFSET(%r8) - movl %edx, BOOT_CTX_EFER_HIGH_OFFSET(%r8) - ret - - .text - .align 8 - .global boot_context -boot_context: - .rept SIZE_OF_BOOT_CTX - .byte 0x00 - .endr diff --git a/hypervisor/boot/guest/vboot_info.c b/hypervisor/boot/guest/vboot_info.c index df5ebfa66..605fad50a 100644 --- a/hypervisor/boot/guest/vboot_info.c +++ b/hypervisor/boot/guest/vboot_info.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/hypervisor/include/arch/x86/boot/boot_context.h b/hypervisor/include/arch/x86/boot/boot_context.h deleted file mode 100644 index ec8a2447e..000000000 --- a/hypervisor/include/arch/x86/boot/boot_context.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2018 Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef BOOT_CTX_H -#define BOOT_CTX_H - -#ifdef ASSEMBLER -#define BOOT_CTX_CR0_OFFSET 176 -#define BOOT_CTX_CR3_OFFSET 192 -#define BOOT_CTX_CR4_OFFSET 184 -#define BOOT_CTX_IDT_OFFSET 144 -#define BOOT_CTX_GDT_OFFSET 128 -#define BOOT_CTX_LDT_SEL_OFFSET 280 -#define BOOT_CTX_TR_SEL_OFFSET 282 -#define BOOT_CTX_CS_SEL_OFFSET 268 -#define BOOT_CTX_SS_SEL_OFFSET 270 -#define BOOT_CTX_DS_SEL_OFFSET 272 -#define BOOT_CTX_ES_SEL_OFFSET 274 -#define BOOT_CTX_FS_SEL_OFFSET 276 -#define BOOT_CTX_GS_SEL_OFFSET 278 -#define BOOT_CTX_CS_AR_OFFSET 248 -#define BOOT_CTX_CS_LIMIT_OFFSET 252 -#define BOOT_CTX_EFER_LOW_OFFSET 200 -#define BOOT_CTX_EFER_HIGH_OFFSET 204 -#define SIZE_OF_BOOT_CTX 296 -#else -#define BOOT_CTX_CR0_OFFSET 176U -#define BOOT_CTX_CR3_OFFSET 192U -#define BOOT_CTX_CR4_OFFSET 184U -#define BOOT_CTX_IDT_OFFSET 144U -#define BOOT_CTX_GDT_OFFSET 128U -#define BOOT_CTX_LDT_SEL_OFFSET 280U -#define BOOT_CTX_TR_SEL_OFFSET 282U -#define BOOT_CTX_CS_SEL_OFFSET 268U -#define BOOT_CTX_SS_SEL_OFFSET 270U -#define BOOT_CTX_DS_SEL_OFFSET 272U -#define BOOT_CTX_ES_SEL_OFFSET 274U -#define BOOT_CTX_FS_SEL_OFFSET 276U -#define BOOT_CTX_GS_SEL_OFFSET 278U -#define BOOT_CTX_CS_AR_OFFSET 248U -#define BOOT_CTX_CS_LIMIT_OFFSET 252U -#define BOOT_CTX_EFER_LOW_OFFSET 200U -#define BOOT_CTX_EFER_HIGH_OFFSET 204U -#define SIZE_OF_BOOT_CTX 296U -struct acrn_vcpu_regs; -extern struct acrn_vcpu_regs boot_context; -#endif /* ASSEMBLER */ -#endif /* BOOT_CTX_H */ diff --git a/misc/hv_prebuild/static_checks.c b/misc/hv_prebuild/static_checks.c index 971d216be..ba23313eb 100644 --- a/misc/hv_prebuild/static_checks.c +++ b/misc/hv_prebuild/static_checks.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -36,23 +35,6 @@ typedef int32_t CAT_(CTA_DummyType,__LINE__)[(expr) ? 1 : -1] /* Build time sanity checks to make sure hard-coded offset * is matching the actual offset! */ -CTASSERT(BOOT_CTX_CR0_OFFSET == offsetof(struct acrn_vcpu_regs, cr0)); -CTASSERT(BOOT_CTX_CR3_OFFSET == offsetof(struct acrn_vcpu_regs, cr3)); -CTASSERT(BOOT_CTX_CR4_OFFSET == offsetof(struct acrn_vcpu_regs, cr4)); -CTASSERT(BOOT_CTX_IDT_OFFSET == offsetof(struct acrn_vcpu_regs, idt)); -CTASSERT(BOOT_CTX_GDT_OFFSET == offsetof(struct acrn_vcpu_regs, gdt)); -CTASSERT(BOOT_CTX_LDT_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ldt_sel)); -CTASSERT(BOOT_CTX_TR_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, tr_sel)); -CTASSERT(BOOT_CTX_CS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, cs_sel)); -CTASSERT(BOOT_CTX_SS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ss_sel)); -CTASSERT(BOOT_CTX_DS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ds_sel)); -CTASSERT(BOOT_CTX_ES_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, es_sel)); -CTASSERT(BOOT_CTX_FS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, fs_sel)); -CTASSERT(BOOT_CTX_GS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, gs_sel)); -CTASSERT(BOOT_CTX_CS_AR_OFFSET == offsetof(struct acrn_vcpu_regs, cs_ar)); -CTASSERT(BOOT_CTX_EFER_LOW_OFFSET == offsetof(struct acrn_vcpu_regs, ia32_efer)); -CTASSERT(BOOT_CTX_EFER_HIGH_OFFSET == offsetof(struct acrn_vcpu_regs, ia32_efer) + 4); - CTASSERT(CPU_CONTEXT_OFFSET_RAX == offsetof(struct acrn_gp_regs, rax)); CTASSERT(CPU_CONTEXT_OFFSET_RBX == offsetof(struct acrn_gp_regs, rbx)); CTASSERT(CPU_CONTEXT_OFFSET_RCX == offsetof(struct acrn_gp_regs, rcx));