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https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-09-20 16:28:10 +00:00
HV: remove vdev ops for partition mode
Remove vdev ops for partition mode, change related code to directly call the corresponding functions instead Remove struct pci_vdev_ops from vpci.h Add @pre for pci_find_vdev_by_pbdf and pci_find_vdev_by_vbdf/partition_mode_vpci_init Change the return value from int32_t to void to comply with misra c and add ASSERT/panic in the functions (if necessary): vdev_hostbridge_init vdev_hostbridge_deinit vdev_pt_init vdev_pt_deinit Still use pr_err in partition_mode_cfgread and partition_mode_cfgwrite to check if vdev cfgread/cfgwrite access is aligned on 1/2/4 bytes, which is the only case that vdev cfgread/cfgwrite will return nonzero, pr_err will be removed in subsequent patch titled "unify the sharing mode and partition mode coding style for similar functions" Remove @pre for local variables Add ASSERT in partition_mode_pdev_init to check if pdev is NULL (user config error) Tracked-On: #2534 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@@ -42,33 +42,31 @@ static inline uint32_t pci_bar_base(uint32_t bar)
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return bar & PCIM_BAR_MEM_BASE;
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}
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static int32_t vdev_pt_init_validate(struct pci_vdev *vdev)
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static int32_t validate(const struct pci_vdev *vdev)
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{
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uint32_t idx;
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int32_t ret = 0;
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for (idx = 0U; idx < PCI_BAR_COUNT; idx++) {
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if ((vdev->bar[idx].base != 0x0UL)
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|| ((vdev->bar[idx].size & 0xFFFUL) != 0x0UL)
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|| ((vdev->bar[idx].type != PCIBAR_MEM32)
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&& (vdev->bar[idx].type != PCIBAR_NONE))) {
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return -EINVAL;
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ret = -EINVAL;
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break;
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}
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}
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return 0;
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return ret;
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}
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int32_t vdev_pt_init(struct pci_vdev *vdev)
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void vdev_pt_init(struct pci_vdev *vdev)
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{
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int32_t ret;
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struct acrn_vm *vm = vdev->vpci->vm;
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uint16_t pci_command;
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ret = vdev_pt_init_validate(vdev);
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if (ret != 0) {
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pr_err("Error, invalid bar defined");
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return ret;
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}
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ASSERT(validate(vdev) == 0, "Error, invalid bar defined");
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/* Create an iommu domain for target VM if not created */
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if (vm->iommu == NULL) {
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@@ -82,24 +80,26 @@ int32_t vdev_pt_init(struct pci_vdev *vdev)
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ret = assign_iommu_device(vm->iommu, (uint8_t)vdev->pdev->bdf.bits.b,
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(uint8_t)(vdev->pdev->bdf.value & 0xFFU));
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if (ret != 0) {
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panic("failed to assign iommu device!");
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}
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pci_command = (uint16_t)pci_pdev_read_cfg(vdev->pdev->bdf, PCIR_COMMAND, 2U);
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/* Disable INTX */
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pci_command |= 0x400U;
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pci_pdev_write_cfg(vdev->pdev->bdf, PCIR_COMMAND, 2U, pci_command);
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return ret;
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}
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int32_t vdev_pt_deinit(const struct pci_vdev *vdev)
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void vdev_pt_deinit(const struct pci_vdev *vdev)
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{
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int32_t ret;
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struct acrn_vm *vm = vdev->vpci->vm;
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ret = unassign_iommu_device(vm->iommu, (uint8_t)vdev->pdev->bdf.bits.b,
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(uint8_t)(vdev->pdev->bdf.value & 0xFFU));
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return ret;
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if (ret != 0) {
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panic("failed to unassign iommu device!");
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}
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}
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int32_t vdev_pt_cfgread(const struct pci_vdev *vdev, uint32_t offset,
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@@ -200,10 +200,3 @@ int32_t vdev_pt_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
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return 0;
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}
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const struct pci_vdev_ops pci_ops_vdev_pt = {
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.init = vdev_pt_init,
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.deinit = vdev_pt_deinit,
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.cfgwrite = vdev_pt_cfgwrite,
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.cfgread = vdev_pt_cfgread,
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};
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