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hv: pirq: clean up irq handlers

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There are several similar irq handlers with confusing function names and it's
not friendly to call update_irq_handler() to update a proper handler after
request_irq().

With this commit, a single generic irq handler is being used, in which, no lock
need to be acquired because our design could guarantee there is no concurrent
irq handling and irq handler request/free.
A flags field is added to irq_desc struct to select the proper processing flow
for an irq. Irqflags is defined as follows:
 IRQF_NONE       (0U)
 IRQF_LEVEL      (1U << 1U)       /* 1: level trigger; 0: edge trigger */
 IRQF_PT         (1U << 2U)       /* 1: for passthrough dev */

Because we have only one irq handler, update_irq_handler() should be replace by
set_irq_trigger_mode(), whichs set trigger mode flag of a certian irq.
Accordingly, the code where called update_irq_handler() need to be updated.

Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Yan, Like
2018-08-16 20:21:11 +08:00
committed by lijinxia
parent 2c044e0c4e
commit a8cd6925fc
8 changed files with 57 additions and 158 deletions
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4
hypervisor/arch/x86/ioapic.c
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@@ -219,9 +219,9 @@ static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
ioapic_set_rte_entry(addr, gsi_table[gsi].pin, rte);
if ((rte.full & IOAPIC_RTE_TRGRMOD) != 0UL) {
update_irq_handler(gsi, handle_level_interrupt_common);
set_irq_trigger_mode(gsi, true);
} else {
update_irq_handler(gsi, common_handler_edge);
set_irq_trigger_mode(gsi, false);
}
dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",