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HV:treewide:Update return type of function ffs64 and ffz64

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To reduce type conversion in HV:
Update return type of function ffs64 and ffz64 as uint16;
For ffs64, when the input is zero, INVALID_BIT_INDEX is returned;
Update temporary variable type and return value check of caller
when it call ffs64 or ffz64;

Note: In the allocate_mem, there is no return value checking for
calling ffz64, this will be updated latter.

V1-->V2:
        INVALID_BIT_INDEX instead of INVALID_NUMBER
        Coding style fixing;
        INVALID_CPU_ID instead of INVALID_PCPU_ID or INVALID_VCPU_ID;
        "%hu" is used to print vcpu id (uint16_t);
        Add "U/UL" for constant value as needed.
V2-->V3:
        ffs64 return INVALID_BIT_INDEX directly when
        the input value is zero;
        Remove excess "%hu" updates.
V3-->V4:
        Clean up the comments of ffs64;
        Add "U" for constant value as needed.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Xiangyang Wu
2018-07-02 14:05:58 +08:00
committed by lijinxia
parent db01efa047
commit a97593e7db
14 changed files with 68 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
hypervisor/include/arch/x86/cpu.h
View File

@@ -211,6 +211,20 @@ enum feature_word {
FEATURE_WORDS,
};
/**
*The invalid cpu_id (INVALID_CPU_ID) is error
*code for error handling, this means that
*caller can't find a valid physical cpu
*or virtual cpu.
*/
#define INVALID_CPU_ID 0xffffU
/**
*The broadcast id (BROADCAST_CPU_ID)
*used to notify all valid phyiscal cpu
*or virtual cpu.
*/
#define BROADCAST_CPU_ID 0xfffeU
/* CPU states defined */
enum cpu_state {
CPU_STATE_RESET = 0,

9
hypervisor/include/arch/x86/cpuid.h
View File

@@ -96,15 +96,6 @@
#define CPUID_EXTEND_FUNCTION_4 0x80000004
#define CPUID_EXTEND_ADDRESS_SIZE 0x80000008
/**pcpu id type is uint16_t,
*The broadcast id (BROADCAST_PCPU_ID)
* used to notify all valid pcpu,
*the invalid pcpu id (INVALID_PCPU_ID) is error
*code for error handling.
*/
#define INVALID_PCPU_ID 0xffffU
#define BROADCAST_PCPU_ID 0xfffeU
static inline void __cpuid(uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)

2
hypervisor/include/arch/x86/guest/vlapic.h
View File

@@ -89,7 +89,7 @@ vlapic_intr_edge(struct vcpu *vcpu, uint32_t vector)
* Triggers the LAPIC local interrupt (LVT) 'vector' on 'cpu'. 'cpu' can
* be set to -1 to trigger the interrupt on all CPUs.
*/
int vlapic_set_local_intr(struct vm *vm, int vcpu_id, uint32_t vector);
int vlapic_set_local_intr(struct vm *vm, uint16_t vcpu_id, uint32_t vector);
int vlapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg);

6
hypervisor/include/arch/x86/softirq.h
View File

@@ -7,9 +7,9 @@
#ifndef SOFTIRQ_H
#define SOFTIRQ_H
#define SOFTIRQ_TIMER 0
#define SOFTIRQ_DEV_ASSIGN 1
#define SOFTIRQ_MAX 2
#define SOFTIRQ_TIMER 0U
#define SOFTIRQ_DEV_ASSIGN 1U
#define SOFTIRQ_MAX 2U
#define SOFTIRQ_MASK ((1UL<<SOFTIRQ_MAX)-1)
/* used for atomic value for prevent recursive */

23
hypervisor/include/lib/bits.h
View File

@@ -91,10 +91,11 @@ static inline uint16_t fls64(uint64_t value)
* and return the index of that bit.
*
* Bits are numbered starting at 0,the least significant bit.
* A return value of -1 means that the argument was zero.
* A return value of INVALID_BIT_INDEX means that the return value is the inalid
* bit index when the input argument was zero.
*
* Examples:
* ffs64 (0x0) = -1
* ffs64 (0x0) = INVALID_BIT_INDEX
* ffs64 (0x01) = 0
* ffs64 (0xf0) = 4
* ffs64 (0xf00) = 8
@@ -104,20 +105,24 @@ static inline uint16_t fls64(uint64_t value)
*
* @param value: 'unsigned long' type value
*
* @return value: zero-based bit index, -1 means 'value' was zero.
* @return value: zero-based bit index, INVALID_BIT_INDEX means
* when 'value' was zero, bit operations function can't find bit
* set and return the invalid bit index directly.
*
* **/
static inline int ffs64(unsigned long value)
static inline uint16_t ffs64(uint64_t value)
{
int ret;
asm volatile("bsfq %1,%q0"
uint64_t ret = 0UL;
if (value == 0UL)
return (INVALID_BIT_INDEX);
asm volatile("bsfq %1,%0"
: "=r" (ret)
: "rm" (value), "0" (-1));
return ret;
: "rm" (value));
return (uint16_t)ret;
}
/*bit scan forward for the least significant bit '0'*/
static inline int ffz64(unsigned long value)
static inline uint16_t ffz64(uint64_t value)
{
return ffs64(~value);
}

2
hypervisor/include/lib/mem_mgt.h
View File

@@ -8,7 +8,7 @@
#define __MEM_MGT_H__
/* Macros */
#define BITMAP_WORD_SIZE 32
#define BITMAP_WORD_SIZE 32U
struct mem_pool {
void *start_addr; /* Start Address of Memory Pool */