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HV:misc:fix "signed/unsigned conversion with cast"

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Signed/unsigned conversion should add cast explicitily
or change the type of them to the same.

V1->V2:Fixed the 0U to 0UL because of the mistakes.
V2->V3:remove unsed macro

Signed-off-by: HuiHuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Huihuang Shi
2018-07-16 12:08:59 +08:00
committed by lijinxia
parent 619c600021
commit aa5027a30c
12 changed files with 95 additions and 92 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/include/arch/x86/assign.h
View File

@@ -9,7 +9,7 @@
#include <ptdev.h>
void ptdev_intx_ack(struct vm *vm, int virt_pin,
void ptdev_intx_ack(struct vm *vm, uint8_t virt_pin,
enum ptdev_vpin_source vpin_src);
int ptdev_msix_remap(struct vm *vm, uint16_t virt_bdf,
struct ptdev_msi_info *info);

2
hypervisor/include/arch/x86/guest/vcpu.h
View File

@@ -13,7 +13,7 @@
#define REG_SIZE 8
/* Number of GPRs saved / restored for guest in VCPU structure */
#define NUM_GPRS 15
#define NUM_GPRS 15U
#define GUEST_STATE_AREA_SIZE 512
#define CPU_CONTEXT_INDEX_RAX 0

38
hypervisor/include/arch/x86/vtd.h
View File

@@ -41,31 +41,31 @@
/*
* Decoding Capability Register
*/
#define iommu_cap_pi(c) (((c) >> 59) & 1UL)
#define iommu_cap_read_drain(c) (((c) >> 55) & 1UL)
#define iommu_cap_write_drain(c) (((c) >> 54) & 1UL)
#define iommu_cap_max_amask_val(c) (((c) >> 48) & 0x3fUL)
#define iommu_cap_num_fault_regs(c) ((((c) >> 40) & 0xffUL) + 1)
#define iommu_cap_pgsel_inv(c) (((c) >> 39) & 1UL)
#define iommu_cap_pi(c) (((c) >> 59U) & 1UL)
#define iommu_cap_read_drain(c) (((c) >> 55U) & 1UL)
#define iommu_cap_write_drain(c) (((c) >> 54U) & 1UL)
#define iommu_cap_max_amask_val(c) (((c) >> 48U) & 0x3fUL)
#define iommu_cap_num_fault_regs(c) ((((c) >> 40U) & 0xffUL) + 1UL)
#define iommu_cap_pgsel_inv(c) (((c) >> 39U) & 1UL)
#define iommu_cap_super_page_val(c) (((c) >> 34) & 0xfUL)
#define iommu_cap_super_page_val(c) (((c) >> 34U) & 0xfUL)
#define iommu_cap_super_offset(c) \
(((find_first_bit(&iommu_cap_super_page_val(c), 4)) \
* OFFSET_STRIDE) + 21)
#define iommu_cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ffUL) * 16)
#define iommu_cap_fault_reg_offset(c) ((((c) >> 24U) & 0x3ffUL) * 16UL)
#define iommu_cap_max_fault_reg_offset(c) \
(iommu_cap_fault_reg_offset(c) + iommu_cap_num_fault_regs(c) * 16)
(iommu_cap_fault_reg_offset(c) + iommu_cap_num_fault_regs(c) * 16UL)
#define iommu_cap_zlr(c) (((c) >> 22) & 1UL)
#define iommu_cap_isoch(c) (((c) >> 23) & 1UL)
#define iommu_cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1UL)
#define iommu_cap_sagaw(c) (((c) >> 8) & 0x1fUL)
#define iommu_cap_caching_mode(c) (((c) >> 7) & 1UL)
#define iommu_cap_phmr(c) (((c) >> 6) & 1UL)
#define iommu_cap_plmr(c) (((c) >> 5) & 1UL)
#define iommu_cap_rwbf(c) (((c) >> 4) & 1UL)
#define iommu_cap_afl(c) (((c) >> 3) & 1UL)
#define iommu_cap_zlr(c) (((c) >> 22U) & 1UL)
#define iommu_cap_isoch(c) (((c) >> 23U) & 1UL)
#define iommu_cap_mgaw(c) ((((c) >> 16U) & 0x3f) + 1UL)
#define iommu_cap_sagaw(c) (((c) >> 8U) & 0x1fUL)
#define iommu_cap_caching_mode(c) (((c) >> 7U) & 1UL)
#define iommu_cap_phmr(c) (((c) >> 6U) & 1UL)
#define iommu_cap_plmr(c) (((c) >> 5U) & 1UL)
#define iommu_cap_rwbf(c) (((c) >> 4U) & 1UL)
#define iommu_cap_afl(c) (((c) >> 3U) & 1UL)
#define iommu_cap_ndoms(c) ((1U) << (4U + 2U * ((c) & 0x7U)))
/*
@@ -218,7 +218,7 @@ int unassign_iommu_device(struct iommu_domain *domain,
/* Create a iommu domain for a VM specified by vm_id */
struct iommu_domain *create_iommu_domain(uint16_t vm_id,
uint64_t translation_table, int addr_width);
uint64_t translation_table, uint32_t addr_width);
/* Destroy the iommu domain */
int destroy_iommu_domain(struct iommu_domain *domain);