diff --git a/hypervisor/arch/x86/assign.c b/hypervisor/arch/x86/assign.c index 7f2e382d7..de3209916 100644 --- a/hypervisor/arch/x86/assign.c +++ b/hypervisor/arch/x86/assign.c @@ -202,7 +202,7 @@ static void ptdev_build_physical_msi(struct vm *vm, struct ptdev_msi_info *info, bool phys; /* get physical destination cpu mask */ - dest = (info->vmsi_addr >> 12) & 0xff; + dest = (info->vmsi_addr >> 12) & 0xffU; phys = ((info->vmsi_addr & (MSI_ADDR_RH | MSI_ADDR_LOG)) != (MSI_ADDR_RH | MSI_ADDR_LOG)); @@ -216,12 +216,12 @@ static void ptdev_build_physical_msi(struct vm *vm, struct ptdev_msi_info *info, /* update physical delivery mode & vector */ info->pmsi_data = info->vmsi_data; - info->pmsi_data &= ~0x7FF; + info->pmsi_data &= ~0x7FFU; info->pmsi_data |= delmode | vector; /* update physical dest mode & dest field */ info->pmsi_addr = info->vmsi_addr; - info->pmsi_addr &= ~0xFF00C; + info->pmsi_addr &= ~0xFF00CU; info->pmsi_addr |= pdmask << 12 | MSI_ADDR_RH | MSI_ADDR_LOG; @@ -636,7 +636,7 @@ int ptdev_msix_remap(struct vm *vm, uint16_t virt_bdf, /* build physical config MSI, update to info->pmsi_xxx */ ptdev_build_physical_msi(vm, info, dev_to_vector(entry->node)); entry->ptdev_intr_info.msi = *info; - entry->ptdev_intr_info.msi.virt_vector = info->vmsi_data & 0xFF; + entry->ptdev_intr_info.msi.virt_vector = info->vmsi_data & 0xFFU; entry->ptdev_intr_info.msi.phys_vector = dev_to_vector(entry->node); /* update irq handler according to info in guest */ @@ -644,9 +644,9 @@ int ptdev_msix_remap(struct vm *vm, uint16_t virt_bdf, dev_dbg(ACRN_DBG_IRQ, "PCI %x:%x.%x MSI VR[%d] 0x%x->0x%x assigned to vm%d", - (entry->virt_bdf >> 8) & 0xFF, - (entry->virt_bdf >> 3) & 0x1F, - (entry->virt_bdf) & 0x7, + (entry->virt_bdf >> 8) & 0xFFU, + (entry->virt_bdf >> 3) & 0x1FU, + (entry->virt_bdf) & 0x7U, entry->ptdev_intr_info.msi.msix_entry_index, entry->ptdev_intr_info.msi.virt_vector, entry->ptdev_intr_info.msi.phys_vector, @@ -920,7 +920,7 @@ static void get_entry_info(struct ptdev_remapping_info *entry, char *type, if (is_entry_active(entry)) { if (entry->type == PTDEV_INTR_MSI) { strcpy_s(type, 16, "MSI"); - *dest = (entry->ptdev_intr_info.msi.pmsi_addr & 0xFF000) + *dest = (entry->ptdev_intr_info.msi.pmsi_addr & 0xFF000U) >> 12; if ((entry->ptdev_intr_info.msi.pmsi_data & APIC_TRIGMOD_LEVEL) != 0U) @@ -1003,10 +1003,10 @@ void get_ptdev_info(char *str, int str_max) is_entry_active(entry) ? (lvl_tm ? "level" : "edge") : "none", pin, vpin, - (bdf & 0xff00) >> 8, - (bdf & 0xf8) >> 3, bdf & 0x7, - (vbdf & 0xff00) >> 8, - (vbdf & 0xf8) >> 3, vbdf & 0x7); + (bdf & 0xff00U) >> 8, + (bdf & 0xf8U) >> 3, bdf & 0x7U, + (vbdf & 0xff00U) >> 8, + (vbdf & 0xf8U) >> 3, vbdf & 0x7U); size -= len; str += len; } diff --git a/hypervisor/arch/x86/guest/guest.c b/hypervisor/arch/x86/guest/guest.c index 318afd494..0d46521c3 100644 --- a/hypervisor/arch/x86/guest/guest.c +++ b/hypervisor/arch/x86/guest/guest.c @@ -31,7 +31,7 @@ struct page_walk_info { inline bool is_vm0(struct vm *vm) { - return (vm->attr.boot_idx & 0x7F) == 0; + return (vm->attr.boot_idx & 0x7FU) == 0; } inline struct vcpu *vcpu_from_vid(struct vm *vm, int vcpu_id) @@ -206,14 +206,14 @@ static int _gva2gpa_pae(struct vcpu *vcpu, struct page_walk_info *pw_info, uint64_t addr; int ret; - addr = pw_info->top_entry & 0xFFFFFFF0UL; + addr = pw_info->top_entry & 0xFFFFFFF0U; base = GPA2HVA(vcpu->vm, addr); if (base == NULL) { ret = -EFAULT; goto out; } - index = (gva >> 30) & 0x3; + index = (gva >> 30) & 0x3UL; entry = base[index]; if ((entry & MMU_32BIT_PDE_P) == 0U) { @@ -264,7 +264,7 @@ int gva2gpa(struct vcpu *vcpu, uint64_t gva, uint64_t *gpa, pw_info.level = pm; pw_info.is_write_access = !!(*err_code & PAGE_FAULT_WR_FLAG); pw_info.is_inst_fetch = !!(*err_code & PAGE_FAULT_ID_FLAG); - pw_info.is_user_mode = ((exec_vmread(VMX_GUEST_CS_SEL) & 0x3) == 3); + pw_info.is_user_mode = ((exec_vmread(VMX_GUEST_CS_SEL) & 0x3UL) == 3UL); pw_info.pse = true; pw_info.nxe = cur_context->ia32_efer & MSR_IA32_EFER_NXE_BIT; pw_info.wp = !!(cur_context->cr0 & CR0_WP); @@ -418,7 +418,7 @@ void init_e820(void) struct multiboot_info *mbi = (struct multiboot_info *)((uint64_t)boot_regs[1]); pr_info("Multiboot info detected\n"); - if ((mbi->mi_flags & 0x40) != 0U) { + if ((mbi->mi_flags & 0x40U) != 0U) { struct multiboot_mmap *mmap = (struct multiboot_mmap *) ((uint64_t)mbi->mi_mmap_addr); diff --git a/hypervisor/arch/x86/guest/instr_emul.c b/hypervisor/arch/x86/guest/instr_emul.c index 8c6751ca2..92469541b 100644 --- a/hypervisor/arch/x86/guest/instr_emul.c +++ b/hypervisor/arch/x86/guest/instr_emul.c @@ -55,11 +55,11 @@ enum { }; /* struct vie_op.op_flags */ -#define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */ -#define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */ -#define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */ -#define VIE_OP_F_NO_MODRM (1 << 3) -#define VIE_OP_F_NO_GLA_VERIFICATION (1 << 4) +#define VIE_OP_F_IMM (1U << 0) /* 16/32-bit immediate operand */ +#define VIE_OP_F_IMM8 (1U << 1) /* 8-bit immediate operand */ +#define VIE_OP_F_MOFFSET (1U << 2) /* 16/32/64-bit immediate moffset */ +#define VIE_OP_F_NO_MODRM (1U << 3) +#define VIE_OP_F_NO_GLA_VERIFICATION (1U << 4) static const struct vie_op two_byte_opcodes[256] = { [0xB6] = { @@ -272,9 +272,9 @@ vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr) * %ah, %ch, %dh and %bh respectively. */ if (vie->rex_present == 0U) { - if ((vie->reg & 0x4) != 0U) { + if ((vie->reg & 0x4U) != 0U) { *lhbr = 1; - *reg = gpr_map[vie->reg & 0x3]; + *reg = gpr_map[vie->reg & 0x3U]; } } } @@ -1343,7 +1343,7 @@ emulate_push(struct vcpu *vcpu, uint64_t mmio_gpa, struct vie *vie, * PUSH is part of the group 5 extended opcodes and is identified * by ModRM:reg = b110. */ - if ((vie->reg & 7) != 6) + if ((vie->reg & 7U) != 6) return -EINVAL; error = emulate_stack_op(vcpu, mmio_gpa, vie, paging, memread, @@ -1364,7 +1364,7 @@ emulate_pop(struct vcpu *vcpu, uint64_t mmio_gpa, struct vie *vie, * POP is part of the group 1A extended opcodes and is identified * by ModRM:reg = b000. */ - if ((vie->reg & 7) != 0) + if ((vie->reg & 7U) != 0) return -EINVAL; error = emulate_stack_op(vcpu, mmio_gpa, vie, paging, memread, @@ -1380,16 +1380,16 @@ emulate_group1(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, { int error; - switch (vie->reg & 7) { - case 0x1: /* OR */ + switch (vie->reg & 7U) { + case 0x1U: /* OR */ error = emulate_or(vcpu, gpa, vie, memread, memwrite, memarg); break; - case 0x4: /* AND */ + case 0x4U: /* AND */ error = emulate_and(vcpu, gpa, vie, memread, memwrite, memarg); break; - case 0x7: /* CMP */ + case 0x7U: /* CMP */ error = emulate_cmp(vcpu, gpa, vie, memread, memwrite, memarg); break; @@ -1415,7 +1415,7 @@ emulate_bittest(struct vcpu *vcpu, uint64_t gpa, struct vie *vie, * Currently we only emulate the 'Bit Test' instruction which is * identified by a ModR/M:reg encoding of 100b. */ - if ((vie->reg & 7) != 4) + if ((vie->reg & 7U) != 4) return -EINVAL; error = vie_read_register(vcpu, VM_REG_GUEST_RFLAGS, &rflags); @@ -1607,7 +1607,7 @@ vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg, if ((prot & PROT_READ) != 0) { /* #GP on a read access to a exec-only code segment */ - if ((type & 0xA) == 0x8) + if ((type & 0xAU) == 0x8U) return -1; } @@ -1616,10 +1616,10 @@ vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg, * #GP on a write access to a code segment or a * read-only data segment. */ - if ((type & 0x8) != 0) /* code segment */ + if ((type & 0x8U) != 0) /* code segment */ return -1; - if ((type & 0xA) == 0) /* read-only data seg */ + if ((type & 0xAU) == 0) /* read-only data seg */ return -1; } @@ -1627,7 +1627,7 @@ vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg, * 'desc->limit' is fully expanded taking granularity into * account. */ - if ((type & 0xC) == 0x4) { + if ((type & 0xCU) == 0x4U) { /* expand-down data segment */ low_limit = desc->limit + 1; high_limit = SEG_DESC_DEF32(desc->access) ? @@ -1786,10 +1786,10 @@ decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d) */ if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) { vie->rex_present = 1; - vie->rex_w = (x & 0x8) != 0U ? 1 : 0; - vie->rex_r = (x & 0x4) != 0U ? 1 : 0; - vie->rex_x = (x & 0x2) != 0U ? 1 : 0; - vie->rex_b = (x & 0x1) != 0U ? 1 : 0; + vie->rex_w = (x & 0x8U) != 0U ? 1 : 0; + vie->rex_r = (x & 0x4U) != 0U ? 1 : 0; + vie->rex_x = (x & 0x2U) != 0U ? 1 : 0; + vie->rex_b = (x & 0x1U) != 0U ? 1 : 0; vie_advance(vie); } @@ -1872,9 +1872,9 @@ decode_modrm(struct vie *vie, enum vm_cpu_mode cpu_mode) if (vie_peek(vie, &x) != 0) return -1; - vie->mod = (x >> 6) & 0x3; - vie->rm = (x >> 0) & 0x7; - vie->reg = (x >> 3) & 0x7; + vie->mod = (x >> 6) & 0x3U; + vie->rm = (x >> 0) & 0x7U; + vie->reg = (x >> 3) & 0x7U; /* * A direct addressing mode makes no sense in the context of an EPT @@ -1954,9 +1954,9 @@ decode_sib(struct vie *vie) return -1; /* De-construct the SIB byte */ - vie->ss = (x >> 6) & 0x3; - vie->index = (x >> 3) & 0x7; - vie->base = (x >> 0) & 0x7; + vie->ss = (x >> 6) & 0x3U; + vie->index = (x >> 3) & 0x7U; + vie->base = (x >> 0) & 0x7U; /* Apply the REX prefix modifiers */ vie->index |= vie->rex_x << 3; diff --git a/hypervisor/arch/x86/guest/instr_emul_wrapper.c b/hypervisor/arch/x86/guest/instr_emul_wrapper.c index 7f9ac027c..bc259f600 100644 --- a/hypervisor/arch/x86/guest/instr_emul_wrapper.c +++ b/hypervisor/arch/x86/guest/instr_emul_wrapper.c @@ -259,7 +259,7 @@ static void get_guest_paging_info(struct vcpu *vcpu, struct emul_cnx *emul_cnx) ASSERT(emul_cnx != NULL && vcpu != NULL, "Error in input arguments"); csar = exec_vmread(VMX_GUEST_CS_ATTR); - cpl = (csar >> 5) & 3; + cpl = (csar >> 5) & 3U; emul_cnx->paging.cr3 = vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context].cr3; emul_cnx->paging.cpl = cpl; diff --git a/hypervisor/arch/x86/guest/instr_emul_wrapper.h b/hypervisor/arch/x86/guest/instr_emul_wrapper.h index bf1a2d7d2..14966dee2 100644 --- a/hypervisor/arch/x86/guest/instr_emul_wrapper.h +++ b/hypervisor/arch/x86/guest/instr_emul_wrapper.h @@ -79,23 +79,23 @@ struct vie { struct vie_op op; /* opcode description */ }; -#define PSL_C 0x00000001 /* carry bit */ -#define PSL_PF 0x00000004 /* parity bit */ -#define PSL_AF 0x00000010 /* bcd carry bit */ -#define PSL_Z 0x00000040 /* zero bit */ -#define PSL_N 0x00000080 /* negative bit */ -#define PSL_T 0x00000100 /* trace enable bit */ -#define PSL_I 0x00000200 /* interrupt enable bit */ -#define PSL_D 0x00000400 /* string instruction direction bit */ -#define PSL_V 0x00000800 /* overflow bit */ -#define PSL_IOPL 0x00003000 /* i/o privilege level */ -#define PSL_NT 0x00004000 /* nested task bit */ -#define PSL_RF 0x00010000 /* resume flag bit */ -#define PSL_VM 0x00020000 /* virtual 8086 mode bit */ -#define PSL_AC 0x00040000 /* alignment checking */ -#define PSL_VIF 0x00080000 /* virtual interrupt enable */ -#define PSL_VIP 0x00100000 /* virtual interrupt pending */ -#define PSL_ID 0x00200000 /* identification bit */ +#define PSL_C 0x00000001U /* carry bit */ +#define PSL_PF 0x00000004U /* parity bit */ +#define PSL_AF 0x00000010U /* bcd carry bit */ +#define PSL_Z 0x00000040U /* zero bit */ +#define PSL_N 0x00000080U /* negative bit */ +#define PSL_T 0x00000100U /* trace enable bit */ +#define PSL_I 0x00000200U /* interrupt enable bit */ +#define PSL_D 0x00000400U /* string instruction direction bit */ +#define PSL_V 0x00000800U /* overflow bit */ +#define PSL_IOPL 0x00003000U /* i/o privilege level */ +#define PSL_NT 0x00004000U /* nested task bit */ +#define PSL_RF 0x00010000U /* resume flag bit */ +#define PSL_VM 0x00020000U /* virtual 8086 mode bit */ +#define PSL_AC 0x00040000U /* alignment checking */ +#define PSL_VIF 0x00080000U /* virtual interrupt enable */ +#define PSL_VIP 0x00100000U /* virtual interrupt pending */ +#define PSL_ID 0x00200000U /* identification bit */ /* * The 'access' field has the format specified in Table 21-2 of the Intel @@ -114,13 +114,13 @@ struct seg_desc { /* * Protections are chosen from these bits, or-ed together */ -#define PROT_NONE 0x00 /* no permissions */ -#define PROT_READ 0x01 /* pages can be read */ -#define PROT_WRITE 0x02 /* pages can be written */ -#define PROT_EXEC 0x04 /* pages can be executed */ +#define PROT_NONE 0x00U /* no permissions */ +#define PROT_READ 0x01U /* pages can be read */ +#define PROT_WRITE 0x02U /* pages can be written */ +#define PROT_EXEC 0x04U /* pages can be executed */ -#define SEG_DESC_TYPE(access) ((access) & 0x001f) -#define SEG_DESC_DPL(access) (((access) >> 5) & 0x3) +#define SEG_DESC_TYPE(access) ((access) & 0x001fU) +#define SEG_DESC_DPL(access) (((access) >> 5) & 0x3U) #define SEG_DESC_PRESENT(access) ((((access) & 0x0080U) != 0U) ? 1 : 0) #define SEG_DESC_DEF32(access) ((((access) & 0x4000U) != 0U) ? 1 : 0) #define SEG_DESC_GRANULARITY(access) ((((access) & 0x8000U) != 0U) ? 1 : 0) diff --git a/hypervisor/arch/x86/guest/pm.c b/hypervisor/arch/x86/guest/pm.c index fb5c0a93a..c6f1ca68f 100644 --- a/hypervisor/arch/x86/guest/pm.c +++ b/hypervisor/arch/x86/guest/pm.c @@ -23,7 +23,7 @@ int validate_pstate(struct vm *vm, uint64_t perf_ctl) } for (i = 0; i < px_cnt; i++) { - if ((px_data + i)->control == (perf_ctl & 0xffff)) { + if ((px_data + i)->control == (perf_ctl & 0xffffUL)) { return 0; } } diff --git a/hypervisor/arch/x86/interrupt.c b/hypervisor/arch/x86/interrupt.c index ad92527e6..719dc307b 100644 --- a/hypervisor/arch/x86/interrupt.c +++ b/hypervisor/arch/x86/interrupt.c @@ -6,7 +6,7 @@ #include -#define EXCEPTION_ERROR_CODE_VALID 8 +#define EXCEPTION_ERROR_CODE_VALID 8U #define INTERRPUT_QUEUE_BUFF_SIZE 255 #define ACRN_DBG_INTR 6 @@ -140,7 +140,7 @@ static int vcpu_do_pending_event(struct vcpu *vcpu) } exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD, VMX_INT_INFO_VALID | - (vector & 0xFF)); + (vector & 0xFFU)); vlapic_intr_accepted(vlapic, vector); return 0; @@ -162,10 +162,10 @@ static int vcpu_do_pending_extint(struct vcpu *vcpu) vpic_pending_intr(vcpu->vm, &vector); if (vector <= NR_MAX_VECTOR) { dev_dbg(ACRN_DBG_INTR, "VPIC: to inject PIC vector %d\n", - vector & 0xFF); + vector & 0xFFU); exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD, VMX_INT_INFO_VALID | - (vector & 0xFF)); + (vector & 0xFFU)); vpic_intr_accepted(vcpu->vm, vector); } } @@ -250,7 +250,7 @@ static void _vcpu_inject_exception(struct vcpu *vcpu, uint32_t vector) } exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD, VMX_INT_INFO_VALID | - (exception_type[vector] << 8) | (vector & 0xFF)); + (exception_type[vector] << 8) | (vector & 0xFFU)); vcpu->arch_vcpu.exception_info.exception = VECTOR_INVALID; } @@ -349,7 +349,7 @@ int external_interrupt_vmexit_handler(struct vcpu *vcpu) return -EINVAL; } - ctx.vector = intr_info & 0xFF; + ctx.vector = intr_info & 0xFFU; dispatch_interrupt(&ctx); @@ -504,7 +504,7 @@ int exception_vmexit_handler(struct vcpu *vcpu) /* Obtain VM-Exit information field pg 2912 */ intinfo = exec_vmread(VMX_EXIT_INT_INFO); if ((intinfo & VMX_INT_INFO_VALID) != 0U) { - exception_vector = intinfo & 0xFF; + exception_vector = intinfo & 0xFFU; /* Check if exception caused by the guest is a HW exception. * If the exit occurred due to a HW exception obtain the * error code to be conveyed to get via the stack @@ -514,12 +514,12 @@ int exception_vmexit_handler(struct vcpu *vcpu) /* get current privilege level and fault address */ cpl = exec_vmread(VMX_GUEST_CS_ATTR); - cpl = (cpl >> 5) & 3; + cpl = (cpl >> 5) & 3U; if (cpl < 3) - int_err_code &= ~4; + int_err_code &= ~4U; else - int_err_code |= 4; + int_err_code |= 4U; } } diff --git a/hypervisor/arch/x86/io.c b/hypervisor/arch/x86/io.c index 3113b257d..5770ada6a 100644 --- a/hypervisor/arch/x86/io.c +++ b/hypervisor/arch/x86/io.c @@ -165,10 +165,10 @@ void allow_guest_io_access(struct vm *vm, uint32_t address, uint32_t nbytes) b = vm->arch_vm.iobitmap[0]; for (i = 0; i < nbytes; i++) { - if ((address & 0x8000) != 0U) + if ((address & 0x8000U) != 0U) b = vm->arch_vm.iobitmap[1]; - a = address & 0x7fff; - b[a >> 5] &= ~(1 << (a & 0x1f)); + a = address & 0x7fffU; + b[a >> 5] &= ~(1 << (a & 0x1fU)); address++; } } @@ -181,10 +181,10 @@ static void deny_guest_io_access(struct vm *vm, uint32_t address, uint32_t nbyte b = vm->arch_vm.iobitmap[0]; for (i = 0; i < nbytes; i++) { - if ((address & 0x8000) != 0U) + if ((address & 0x8000U) != 0U) b = vm->arch_vm.iobitmap[1]; - a = address & 0x7fff; - b[a >> 5] |= (1 << (a & 0x1f)); + a = address & 0x7fffU; + b[a >> 5] |= (1 << (a & 0x1fU)); address++; } } diff --git a/hypervisor/arch/x86/timer.c b/hypervisor/arch/x86/timer.c index 76265778e..71763f7b7 100644 --- a/hypervisor/arch/x86/timer.c +++ b/hypervisor/arch/x86/timer.c @@ -243,7 +243,7 @@ static uint64_t pit_calibrate_tsc(uint16_t cal_ms) */ io_write_byte(0x30, 0x43); - io_write_byte(initial_pit & 0x00ff, 0x40); /* Write LSB */ + io_write_byte(initial_pit & 0x00ffU, 0x40); /* Write LSB */ io_write_byte(initial_pit >> 8, 0x40); /* Write MSB */ current_tsc = rdtsc(); diff --git a/hypervisor/arch/x86/trusty.c b/hypervisor/arch/x86/trusty.c index 742d0b20a..d3aacbb8d 100644 --- a/hypervisor/arch/x86/trusty.c +++ b/hypervisor/arch/x86/trusty.c @@ -284,10 +284,10 @@ void switch_world(struct vcpu *vcpu, int next_world) /* load EPTP for next world */ if (next_world == NORMAL_WORLD) { exec_vmwrite64(VMX_EPT_POINTER_FULL, - vcpu->vm->arch_vm.nworld_eptp | (3<<3) | 6); + vcpu->vm->arch_vm.nworld_eptp | (3UL<<3) | 6UL); } else { exec_vmwrite64(VMX_EPT_POINTER_FULL, - vcpu->vm->arch_vm.sworld_eptp | (3<<3) | 6); + vcpu->vm->arch_vm.sworld_eptp | (3UL<<3) | 6UL); } /* Update world index */ @@ -420,7 +420,7 @@ bool initialize_trusty(struct vcpu *vcpu, uint64_t param) trusty_base_hpa = vm->sworld_control.sworld_memory.base_hpa; exec_vmwrite64(VMX_EPT_POINTER_FULL, - vm->arch_vm.sworld_eptp | (3<<3) | 6); + vm->arch_vm.sworld_eptp | (3UL<<3) | 6UL); /* save Normal World context */ save_world_ctx(&vcpu->arch_vcpu.contexts[NORMAL_WORLD]); diff --git a/hypervisor/arch/x86/vmexit.c b/hypervisor/arch/x86/vmexit.c index 68286e58c..01d122104 100644 --- a/hypervisor/arch/x86/vmexit.c +++ b/hypervisor/arch/x86/vmexit.c @@ -145,7 +145,7 @@ int vmexit_handler(struct vcpu *vcpu) /* Filter out HW exception & NMI */ if ((vcpu->arch_vcpu.idt_vectoring_info & VMX_INT_INFO_VALID) != 0U) { uint32_t vector_info = vcpu->arch_vcpu.idt_vectoring_info; - uint32_t vector = vector_info & 0xff; + uint32_t vector = vector_info & 0xffU; uint32_t type = (vector_info & VMX_INT_TYPE_MASK) >> 8; uint32_t err_code = 0; @@ -161,7 +161,7 @@ int vmexit_handler(struct vcpu *vcpu) } /* Calculate basic exit reason (low 16-bits) */ - basic_exit_reason = vcpu->arch_vcpu.exit_reason & 0xFFFF; + basic_exit_reason = vcpu->arch_vcpu.exit_reason & 0xFFFFU; /* Log details for exit */ pr_dbg("Exit Reason: 0x%016llx ", vcpu->arch_vcpu.exit_reason); @@ -327,7 +327,7 @@ static int xsetbv_vmexit_handler(struct vcpu *vcpu) (ctx_ptr->guest_cpu_regs.regs.rdx << 32); /*bit 0(x87 state) of XCR0 can't be cleared*/ - if ((val64 & 0x01) == 0U) { + if ((val64 & 0x01UL) == 0U) { vcpu_inject_gp(vcpu, 0); return -1; } @@ -336,7 +336,7 @@ static int xsetbv_vmexit_handler(struct vcpu *vcpu) *set to 10b as it is necessary to set both bits *to use AVX instructions. **/ - if (((val64 >> 1) & 0x3) == 0x2) { + if (((val64 >> 1) & 0x3UL) == 0x2UL) { vcpu_inject_gp(vcpu, 0); return -1; } diff --git a/hypervisor/boot/acpi.c b/hypervisor/boot/acpi.c index 9d5b704c0..a89ceed66 100644 --- a/hypervisor/boot/acpi.c +++ b/hypervisor/boot/acpi.c @@ -40,7 +40,7 @@ #define RSDP_CHECKSUM_LENGTH 20 #define ACPI_NAME_SIZE 4 #define ACPI_MADT_TYPE_LOCAL_APIC 0 -#define ACPI_MADT_ENABLED 1 +#define ACPI_MADT_ENABLED 1U #define ACPI_OEM_TABLE_ID_SIZE 8 struct acpi_table_rsdp { diff --git a/hypervisor/bsp/sbl/sbl.c b/hypervisor/bsp/sbl/sbl.c index c9ea64f7d..5b79fb977 100644 --- a/hypervisor/bsp/sbl/sbl.c +++ b/hypervisor/bsp/sbl/sbl.c @@ -7,21 +7,21 @@ #include /* IOAPIC id */ -#define SBL_IOAPIC_ID 8 +#define SBL_IOAPIC_ID 8U /* IOAPIC base address */ -#define SBL_IOAPIC_ADDR 0xfec00000 +#define SBL_IOAPIC_ADDR 0xfec00000U /* IOAPIC range size */ -#define SBL_IOAPIC_SIZE 0x100000 +#define SBL_IOAPIC_SIZE 0x100000U /* Local APIC base address */ -#define SBL_LAPIC_ADDR 0xfee00000 +#define SBL_LAPIC_ADDR 0xfee00000U /* Local APIC range size */ -#define SBL_LAPIC_SIZE 0x100000 +#define SBL_LAPIC_SIZE 0x100000U /* Number of PCI IRQ assignments */ #define SBL_PCI_IRQ_ASSIGNMENT_NUM 28 #ifndef CONFIG_DMAR_PARSE_ENABLED static struct dmar_dev_scope default_drhd_unit_dev_scope0[] = { - { .bus = 0, .devfun = DEVFUN(0x2, 0), }, + { .bus = 0U, .devfun = DEVFUN(0x2U, 0U), }, }; static struct dmar_drhd drhd_info_array[] = { diff --git a/hypervisor/bsp/uefi/efi/multiboot.h b/hypervisor/bsp/uefi/efi/multiboot.h index 0f0b03daa..28fcd7187 100644 --- a/hypervisor/bsp/uefi/efi/multiboot.h +++ b/hypervisor/bsp/uefi/efi/multiboot.h @@ -83,19 +83,19 @@ extern struct multiboot_header *Multiboot_Header; /* * Multiboot information structure. */ -#define MULTIBOOT_INFO_MAGIC 0x2BADB002 -#define MULTIBOOT_INFO_HAS_MEMORY 0x00000001 -#define MULTIBOOT_INFO_HAS_BOOT_DEVICE 0x00000002 -#define MULTIBOOT_INFO_HAS_CMDLINE 0x00000004 -#define MULTIBOOT_INFO_HAS_MODS 0x00000008 -#define MULTIBOOT_INFO_HAS_AOUT_SYMS 0x00000010 -#define MULTIBOOT_INFO_HAS_ELF_SYMS 0x00000020 -#define MULTIBOOT_INFO_HAS_MMAP 0x00000040 -#define MULTIBOOT_INFO_HAS_DRIVES 0x00000080 -#define MULTIBOOT_INFO_HAS_CONFIG_TABLE 0x00000100 -#define MULTIBOOT_INFO_HAS_LOADER_NAME 0x00000200 -#define MULTIBOOT_INFO_HAS_APM_TABLE 0x00000400 -#define MULTIBOOT_INFO_HAS_VBE 0x00000800 +#define MULTIBOOT_INFO_MAGIC 0x2BADB002U +#define MULTIBOOT_INFO_HAS_MEMORY 0x00000001U +#define MULTIBOOT_INFO_HAS_BOOT_DEVICE 0x00000002U +#define MULTIBOOT_INFO_HAS_CMDLINE 0x00000004U +#define MULTIBOOT_INFO_HAS_MODS 0x00000008U +#define MULTIBOOT_INFO_HAS_AOUT_SYMS 0x00000010U +#define MULTIBOOT_INFO_HAS_ELF_SYMS 0x00000020U +#define MULTIBOOT_INFO_HAS_MMAP 0x00000040U +#define MULTIBOOT_INFO_HAS_DRIVES 0x00000080U +#define MULTIBOOT_INFO_HAS_CONFIG_TABLE 0x00000100U +#define MULTIBOOT_INFO_HAS_LOADER_NAME 0x00000200U +#define MULTIBOOT_INFO_HAS_APM_TABLE 0x00000400U +#define MULTIBOOT_INFO_HAS_VBE 0x00000800U #if !defined(_LOCORE) struct multiboot_info { diff --git a/hypervisor/common/hv_main.c b/hypervisor/common/hv_main.c index a7b0f57f5..c785d7ca3 100644 --- a/hypervisor/common/hv_main.c +++ b/hypervisor/common/hv_main.c @@ -87,12 +87,12 @@ void vcpu_thread(struct vcpu *vcpu) if (ret < 0) { pr_fatal("dispatch VM exit handler failed for reason" " %d, ret = %d!", - vcpu->arch_vcpu.exit_reason & 0xFFFF, ret); + vcpu->arch_vcpu.exit_reason & 0xFFFFU, ret); vcpu_inject_gp(vcpu, 0); continue; } - basic_exit_reason = vcpu->arch_vcpu.exit_reason & 0xFFFF; + basic_exit_reason = vcpu->arch_vcpu.exit_reason & 0xFFFFU; per_cpu(vmexit_cnt, vcpu->pcpu_id)[basic_exit_reason]++; TRACE_2L(TRACE_VM_EXIT, basic_exit_reason, vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context].rip); diff --git a/hypervisor/common/hypercall.c b/hypervisor/common/hypercall.c index 1680ee936..00a682c46 100644 --- a/hypervisor/common/hypercall.c +++ b/hypervisor/common/hypercall.c @@ -17,7 +17,7 @@ bool is_hypercall_from_ring0(void) cs_sel = exec_vmread(VMX_GUEST_CS_SEL); /* cs_selector[1:0] is CPL */ - if ((cs_sel & 0x3) == 0) + if ((cs_sel & 0x3UL) == 0) return true; return false; @@ -395,7 +395,7 @@ int64_t _set_vm_memmap(struct vm *vm, struct vm *target_vm, uint64_t hpa; uint32_t attr, prot; - if ((memmap->length & 0xFFF) != 0) { + if ((memmap->length & 0xFFFUL) != 0) { pr_err("%s: ERROR! [vm%d] map size 0x%x is not page aligned", __func__, target_vm->attr.id, memmap->length); return -1; @@ -608,7 +608,7 @@ int64_t hcall_assign_ptdev(struct vm *vm, uint64_t vmid, uint64_t param) } ret = assign_iommu_device(target_vm->iommu_domain, - (uint8_t)(bdf >> 8), (uint8_t)(bdf & 0xff)); + (uint8_t)(bdf >> 8), (uint8_t)(bdf & 0xffU)); return ret; } @@ -627,7 +627,7 @@ int64_t hcall_deassign_ptdev(struct vm *vm, uint64_t vmid, uint64_t param) return -1; } ret = unassign_iommu_device(target_vm->iommu_domain, - (uint8_t)(bdf >> 8), (uint8_t)(bdf & 0xff)); + (uint8_t)(bdf >> 8), (uint8_t)(bdf & 0xffU)); return ret; } diff --git a/hypervisor/common/vm_load.c b/hypervisor/common/vm_load.c index 0ac3e18b7..2e1f65ec8 100644 --- a/hypervisor/common/vm_load.c +++ b/hypervisor/common/vm_load.c @@ -57,7 +57,7 @@ static uint64_t create_zero_page(struct vm *vm) /* set constant arguments in zero page */ zeropage->hdr.loader_type = 0xff; - zeropage->hdr.load_flags |= (1 << 5); /* quiet */ + zeropage->hdr.load_flags |= (1U << 5); /* quiet */ /* Create/add e820 table entries in zeropage */ zeropage->e820_nentries = create_e820_table(zeropage->e820); diff --git a/hypervisor/debug/serial_internal.h b/hypervisor/debug/serial_internal.h index df36cfa31..4909ff476 100644 --- a/hypervisor/debug/serial_internal.h +++ b/hypervisor/debug/serial_internal.h @@ -30,21 +30,21 @@ struct shared_buf; #define SD_RX_INTERRUPT 1 /* RX error defines */ -#define SD_RX_NO_ERROR 0 -#define SD_RX_OVERRUN_ERROR 1 -#define SD_RX_PARITY_ERROR 2 -#define SD_RX_FRAME_ERROR 3 +#define SD_RX_NO_ERROR 0U +#define SD_RX_OVERRUN_ERROR 1U +#define SD_RX_PARITY_ERROR 2U +#define SD_RX_FRAME_ERROR 3U /* Defines for encoding/decoding the unique UART handle of each port. */ -#define SERIAL_MAGIC_NUM 0x005500AA +#define SERIAL_MAGIC_NUM 0x005500AAU #define SERIAL_VALIDATE_HANDLE(handle) \ ((handle & 0xFFFF00FF) == (SERIAL_MAGIC_NUM)) #define SERIAL_ENCODE_INDEX(index) ((SERIAL_MAGIC_NUM) | (index << 8)) -#define SERIAL_DECODE_INDEX(handle) ((handle & 0x0000FF00) >> 8) +#define SERIAL_DECODE_INDEX(handle) ((handle & 0x0000FF00U) >> 8) #define NO_SUSPEND 0 -#define SUSPEND 0xFFFFFFFFUL +#define SUSPEND 0xFFFFFFFFU /* Enumeration values to set UART Configuration */ typedef enum _baudenum_ { diff --git a/hypervisor/debug/uart16550.c b/hypervisor/debug/uart16550.c index 21dc0a8a5..48d43f755 100644 --- a/hypervisor/debug/uart16550.c +++ b/hypervisor/debug/uart16550.c @@ -113,9 +113,9 @@ static int uart16550_set_baud_rate(struct tgt_uart *tgt_uart, /* Write the appropriate divisor value */ uart16550_write_reg(tgt_uart->base_address, - ((baud_div >> 8) & 0xFF), DLM_IDX); + ((baud_div >> 8) & 0xFFU), DLM_IDX); uart16550_write_reg(tgt_uart->base_address, - (baud_div & 0xFF), DLL_IDX); + (baud_div & 0xFFU), DLL_IDX); /* Disable DLL and DLM registers */ temp_reg &= ~LCR_DLAB; diff --git a/hypervisor/debug/uart16550.h b/hypervisor/debug/uart16550.h index 68f19651e..f28438115 100644 --- a/hypervisor/debug/uart16550.h +++ b/hypervisor/debug/uart16550.h @@ -8,99 +8,99 @@ #define UART16550_H /* Register / bit definitions for 16c550 uart */ -#define UART16550_RBR 0x00 +#define UART16550_RBR 0x00U /*receive buffer register | base+00h, dlab=0b r*/ -#define UART16550_THR 0x00 +#define UART16550_THR 0x00U /*transmit holding register | base+00h, dlab=0b w*/ -#define UART16550_DLL 0x00 +#define UART16550_DLL 0x00U /*divisor least significant byte | base+00h, dlab=1b rw*/ -#define UART16550_IER 0x01 +#define UART16550_IER 0x01U /*interrupt enable register | base+01h, dlab=0b rw*/ -#define UART16550_DLM 0x01 +#define UART16550_DLM 0x01U /*divisor most significant byte | base+01h, dlab=1b rw*/ -#define UART16550_IIR 0x02 +#define UART16550_IIR 0x02U /*interrupt identification register | base+02h, dlab=0b r*/ -#define UART16550_FCR 0x02 +#define UART16550_FCR 0x02U /*fifo control register | base+02h, dlab=0b w*/ -#define UART16550_LCR 0x03 +#define UART16550_LCR 0x03U /*line control register | base+03h, dlab=xb rw*/ -#define UART16550_MCR 0x04 +#define UART16550_MCR 0x04U /*modem control register, only uart0 | base+04h, dlab=xb rw*/ -#define UART16550_LSR 0x05 +#define UART16550_LSR 0x05U /*line status register | base+05h, dlab=xb r*/ -#define UART16550_MSR 0x06 +#define UART16550_MSR 0x06U /*modem status register, only uart0 | base+06h, dlab=xb r*/ -#define UART16550_SCR 0x07 +#define UART16550_SCR 0x07U /*scratch pad register | base+07h, dlab=xb rw*/ -#define UART16550_MDR1 0x08 -#define UARTML7213_BRCSR 0x0e +#define UART16550_MDR1 0x08U +#define UARTML7213_BRCSR 0x0eU /*baud rate reference clock select register dlab xb*/ -#define UARTML7213_SRST 0x0f /*Soft Reset Register dlab xb*/ +#define UARTML7213_SRST 0x0fU /*Soft Reset Register dlab xb*/ /* value definitions for IIR */ -#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ -#define IIR_RXTOUT 0x0c -#define IIR_RLS 0x06 -#define IIR_RXRDY 0x04 -#define IIR_TXRDY 0x02 -#define IIR_NOPEND 0x01 -#define IIR_MLSC 0x00 +#define IIR_FIFO_MASK 0xc0U /* set if FIFOs are enabled */ +#define IIR_RXTOUT 0x0cU +#define IIR_RLS 0x06U +#define IIR_RXRDY 0x04U +#define IIR_TXRDY 0x02U +#define IIR_NOPEND 0x01U +#define IIR_MLSC 0x00U -#define IER_EDSSI (0x0008) +#define IER_EDSSI (0x0008U) /*enable/disable modem status interrupt*/ -#define IER_ELSI (0x0004) +#define IER_ELSI (0x0004U) /*enable/disable receive data error interrupt*/ -#define IER_ETBEI (0x0002) +#define IER_ETBEI (0x0002U) /*enable/disable transmit data write request interrupt*/ -#define IER_ERBFI (0x0001) +#define IER_ERBFI (0x0001U) /*enable/disable receive data read request interrupt*/ /* definition for LCR */ -#define LCR_DLAB (1 << 7) /*DLAB THR/RBR&IER or DLL&DLM= Bit 7*/ -#define LCR_SB (1 << 6) /*break control on/off= Bit 6*/ -#define LCR_SP (1 << 5) /*Specifies the operation of parity bit*/ -#define LCR_EPS (1 << 4) /*Specifies the logic of a parity bit*/ -#define LCR_PEN (1 << 3) /*Specifies whether to add a parity bit*/ -#define LCR_STB (1 << 2) /*stop bit length*/ -#define LCR_WL8 (0x03) /*number of bits of serial data*/ -#define LCR_WL7 (0x02) /*number of bits of serial data*/ -#define LCR_WL6 (0x01) /*number of bits of serial data*/ -#define LCR_WL5 (0x00) /*number of bits of serial data*/ +#define LCR_DLAB (1U << 7) /*DLAB THR/RBR&IER or DLL&DLM= Bit 7*/ +#define LCR_SB (1U << 6) /*break control on/off= Bit 6*/ +#define LCR_SP (1U << 5) /*Specifies the operation of parity bit*/ +#define LCR_EPS (1U << 4) /*Specifies the logic of a parity bit*/ +#define LCR_PEN (1U << 3) /*Specifies whether to add a parity bit*/ +#define LCR_STB (1U << 2) /*stop bit length*/ +#define LCR_WL8 (0x03U) /*number of bits of serial data*/ +#define LCR_WL7 (0x02U) /*number of bits of serial data*/ +#define LCR_WL6 (0x01U) /*number of bits of serial data*/ +#define LCR_WL5 (0x00U) /*number of bits of serial data*/ #define LCR_PARITY_ODD (LCR_PEN) -#define LCR_PARITY_NONE 0x0 +#define LCR_PARITY_NONE 0x0U #define LCR_PARITY_EVEN (LCR_PEN | LCR_EPS) -#define LCR_NB_STOP_BITS_1 0x0 +#define LCR_NB_STOP_BITS_1 0x0U #define LCR_NB_STOP_BITS_2 (LCR_STB) /* bit definitions for LSR */ /* at least one error in data within fifo */ -#define LSR_ERR (1 << 7) +#define LSR_ERR (1U << 7) /* Transmit data Present */ -#define LSR_TEMT (1 << 6) +#define LSR_TEMT (1U << 6) /* Transmit data write request present */ -#define LSR_THRE (1 << 5) +#define LSR_THRE (1U << 5) /* Break interrupt data Present */ -#define LSR_BI (1 << 4) +#define LSR_BI (1U << 4) /* Framing Error Occurred */ -#define LSR_FE (1 << 3) +#define LSR_FE (1U << 3) /* Parity Error Occurred */ -#define LSR_PE (1 << 2) +#define LSR_PE (1U << 2) /* Overrun error */ -#define LSR_OE (1 << 1) +#define LSR_OE (1U << 1) /* Readable received data is present */ -#define LSR_DR (1 << 0) +#define LSR_DR (1U << 0) /* definition for MCR */ -#define MCR_RTS (1 << 1) /* Request to Send */ -#define MCR_DTR (1 << 0) /* Data Terminal Ready */ +#define MCR_RTS (1U << 1) /* Request to Send */ +#define MCR_DTR (1U << 0) /* Data Terminal Ready */ /* definition for FCR */ -#define FCR_RX_MASK 0xc0 -#define FCR_DMA (1 << 3) -#define FCR_TFR (1 << 2) /* Reset Transmit Fifo */ -#define FCR_RFR (1 << 1) /* Reset Receive Fifo */ -#define FCR_FIFOE (1 << 0) /* Fifo Enable */ +#define FCR_RX_MASK 0xc0U +#define FCR_DMA (1U << 3) +#define FCR_TFR (1U << 2) /* Reset Transmit Fifo */ +#define FCR_RFR (1U << 1) /* Reset Receive Fifo */ +#define FCR_FIFOE (1U << 0) /* Fifo Enable */ -#define UART_IER_DISABLE_ALL 0x00000000 +#define UART_IER_DISABLE_ALL 0x00000000U #endif /* !UART16550_H */ diff --git a/hypervisor/debug/vuart.c b/hypervisor/debug/vuart.c index e1d0418a6..a154447fd 100644 --- a/hypervisor/debug/vuart.c +++ b/hypervisor/debug/vuart.c @@ -179,7 +179,7 @@ static void uart_write(__unused struct vm_io_handler *hdlr, * Apply mask so that bits 4-7 are 0 * Also enables bits 0-3 only if they're 1 */ - vu->ier = value & 0x0F; + vu->ier = value & 0x0FU; break; case UART16550_FCR: /* diff --git a/hypervisor/include/arch/x86/guest/vm.h b/hypervisor/include/arch/x86/guest/vm.h index 688b48758..bb95b13a0 100644 --- a/hypervisor/include/arch/x86/guest/vm.h +++ b/hypervisor/include/arch/x86/guest/vm.h @@ -112,7 +112,7 @@ struct vm_arch { /* reference to virtual platform to come here (as needed) */ }; -#define CPUID_CHECK_SUBLEAF (1 << 0) +#define CPUID_CHECK_SUBLEAF (1U << 0) #define MAX_VM_VCPUID_ENTRIES 64 struct vcpuid_entry { uint32_t eax; diff --git a/hypervisor/include/arch/x86/multiboot.h b/hypervisor/include/arch/x86/multiboot.h index 77fa6166a..13b0a6263 100644 --- a/hypervisor/include/arch/x86/multiboot.h +++ b/hypervisor/include/arch/x86/multiboot.h @@ -7,10 +7,10 @@ #ifndef MULTIBOOT_H #define MULTIBOOT_H -#define MULTIBOOT_INFO_MAGIC 0x2BADB002 -#define MULTIBOOT_INFO_HAS_CMDLINE 0x00000004 -#define MULTIBOOT_INFO_HAS_MODS 0x00000008 -#define MULTIBOOT_INFO_HAS_DRIVES 0x00000080 +#define MULTIBOOT_INFO_MAGIC 0x2BADB002U +#define MULTIBOOT_INFO_HAS_CMDLINE 0x00000004U +#define MULTIBOOT_INFO_HAS_MODS 0x00000008U +#define MULTIBOOT_INFO_HAS_DRIVES 0x00000080U struct multiboot_info { uint32_t mi_flags; diff --git a/hypervisor/include/debug/logmsg.h b/hypervisor/include/debug/logmsg.h index a17ac2beb..af2208d52 100644 --- a/hypervisor/include/debug/logmsg.h +++ b/hypervisor/include/debug/logmsg.h @@ -17,8 +17,8 @@ #define LOG_DEBUG 6 /* Logging flags */ -#define LOG_FLAG_STDOUT 0x00000001 -#define LOG_FLAG_MEMORY 0x00000002 +#define LOG_FLAG_STDOUT 0x00000001U +#define LOG_FLAG_MEMORY 0x00000002U #define LOG_ENTRY_SIZE 80 /* Size of buffer used to store a message being logged, * should align to LOG_ENTRY_SIZE. diff --git a/hypervisor/include/public/acrn_common.h b/hypervisor/include/public/acrn_common.h index f71063e53..186a9421f 100644 --- a/hypervisor/include/public/acrn_common.h +++ b/hypervisor/include/public/acrn_common.h @@ -337,10 +337,10 @@ struct acpi_info { * For Px, PMCMD_STATE_NUM means Px number from 0 to (MAX_PSTATE - 1), * For Cx, PMCMD_STATE_NUM means Cx entry index from 1 to MAX_CX_ENTRY. */ -#define PMCMD_VMID_MASK 0xff000000 -#define PMCMD_VCPUID_MASK 0x00ff0000 -#define PMCMD_STATE_NUM_MASK 0x0000ff00 -#define PMCMD_TYPE_MASK 0x000000ff +#define PMCMD_VMID_MASK 0xff000000U +#define PMCMD_VCPUID_MASK 0x00ff0000U +#define PMCMD_STATE_NUM_MASK 0x0000ff00U +#define PMCMD_TYPE_MASK 0x000000ffU #define PMCMD_VMID_SHIFT 24 #define PMCMD_VCPUID_SHIFT 16 diff --git a/hypervisor/include/public/acrn_hv_defs.h b/hypervisor/include/public/acrn_hv_defs.h index c4f84b9a1..df94126ea 100644 --- a/hypervisor/include/public/acrn_hv_defs.h +++ b/hypervisor/include/public/acrn_hv_defs.h @@ -25,73 +25,73 @@ /* general */ #define HC_ID_GEN_BASE 0x0UL -#define HC_GET_API_VERSION _HC_ID(HC_ID, HC_ID_GEN_BASE + 0x00) +#define HC_GET_API_VERSION _HC_ID(HC_ID, HC_ID_GEN_BASE + 0x00UL) /* VM management */ #define HC_ID_VM_BASE 0x10UL -#define HC_CREATE_VM _HC_ID(HC_ID, HC_ID_VM_BASE + 0x00) -#define HC_DESTROY_VM _HC_ID(HC_ID, HC_ID_VM_BASE + 0x01) -#define HC_START_VM _HC_ID(HC_ID, HC_ID_VM_BASE + 0x02) -#define HC_PAUSE_VM _HC_ID(HC_ID, HC_ID_VM_BASE + 0x03) -#define HC_CREATE_VCPU _HC_ID(HC_ID, HC_ID_VM_BASE + 0x04) +#define HC_CREATE_VM _HC_ID(HC_ID, HC_ID_VM_BASE + 0x00UL) +#define HC_DESTROY_VM _HC_ID(HC_ID, HC_ID_VM_BASE + 0x01UL) +#define HC_START_VM _HC_ID(HC_ID, HC_ID_VM_BASE + 0x02UL) +#define HC_PAUSE_VM _HC_ID(HC_ID, HC_ID_VM_BASE + 0x03UL) +#define HC_CREATE_VCPU _HC_ID(HC_ID, HC_ID_VM_BASE + 0x04UL) /* IRQ and Interrupts */ #define HC_ID_IRQ_BASE 0x20UL -#define HC_ASSERT_IRQLINE _HC_ID(HC_ID, HC_ID_IRQ_BASE + 0x00) -#define HC_DEASSERT_IRQLINE _HC_ID(HC_ID, HC_ID_IRQ_BASE + 0x01) -#define HC_PULSE_IRQLINE _HC_ID(HC_ID, HC_ID_IRQ_BASE + 0x02) -#define HC_INJECT_MSI _HC_ID(HC_ID, HC_ID_IRQ_BASE + 0x03) +#define HC_ASSERT_IRQLINE _HC_ID(HC_ID, HC_ID_IRQ_BASE + 0x00UL) +#define HC_DEASSERT_IRQLINE _HC_ID(HC_ID, HC_ID_IRQ_BASE + 0x01UL) +#define HC_PULSE_IRQLINE _HC_ID(HC_ID, HC_ID_IRQ_BASE + 0x02UL) +#define HC_INJECT_MSI _HC_ID(HC_ID, HC_ID_IRQ_BASE + 0x03UL) /* DM ioreq management */ #define HC_ID_IOREQ_BASE 0x30UL -#define HC_SET_IOREQ_BUFFER _HC_ID(HC_ID, HC_ID_IOREQ_BASE + 0x00) -#define HC_NOTIFY_REQUEST_FINISH _HC_ID(HC_ID, HC_ID_IOREQ_BASE + 0x01) +#define HC_SET_IOREQ_BUFFER _HC_ID(HC_ID, HC_ID_IOREQ_BASE + 0x00UL) +#define HC_NOTIFY_REQUEST_FINISH _HC_ID(HC_ID, HC_ID_IOREQ_BASE + 0x01UL) /* Guest memory management */ #define HC_ID_MEM_BASE 0x40UL -#define HC_VM_SET_MEMMAP _HC_ID(HC_ID, HC_ID_MEM_BASE + 0x00) -#define HC_VM_GPA2HPA _HC_ID(HC_ID, HC_ID_MEM_BASE + 0x01) -#define HC_VM_SET_MEMMAPS _HC_ID(HC_ID, HC_ID_MEM_BASE + 0x02) +#define HC_VM_SET_MEMMAP _HC_ID(HC_ID, HC_ID_MEM_BASE + 0x00UL) +#define HC_VM_GPA2HPA _HC_ID(HC_ID, HC_ID_MEM_BASE + 0x01UL) +#define HC_VM_SET_MEMMAPS _HC_ID(HC_ID, HC_ID_MEM_BASE + 0x02UL) /* PCI assignment*/ #define HC_ID_PCI_BASE 0x50UL -#define HC_ASSIGN_PTDEV _HC_ID(HC_ID, HC_ID_PCI_BASE + 0x00) -#define HC_DEASSIGN_PTDEV _HC_ID(HC_ID, HC_ID_PCI_BASE + 0x01) -#define HC_VM_PCI_MSIX_REMAP _HC_ID(HC_ID, HC_ID_PCI_BASE + 0x02) -#define HC_SET_PTDEV_INTR_INFO _HC_ID(HC_ID, HC_ID_PCI_BASE + 0x03) -#define HC_RESET_PTDEV_INTR_INFO _HC_ID(HC_ID, HC_ID_PCI_BASE + 0x04) +#define HC_ASSIGN_PTDEV _HC_ID(HC_ID, HC_ID_PCI_BASE + 0x00UL) +#define HC_DEASSIGN_PTDEV _HC_ID(HC_ID, HC_ID_PCI_BASE + 0x01UL) +#define HC_VM_PCI_MSIX_REMAP _HC_ID(HC_ID, HC_ID_PCI_BASE + 0x02UL) +#define HC_SET_PTDEV_INTR_INFO _HC_ID(HC_ID, HC_ID_PCI_BASE + 0x03UL) +#define HC_RESET_PTDEV_INTR_INFO _HC_ID(HC_ID, HC_ID_PCI_BASE + 0x04UL) /* DEBUG */ #define HC_ID_DBG_BASE 0x60UL -#define HC_SETUP_SBUF _HC_ID(HC_ID, HC_ID_DBG_BASE + 0x00) +#define HC_SETUP_SBUF _HC_ID(HC_ID, HC_ID_DBG_BASE + 0x00UL) /* Trusty */ #define HC_ID_TRUSTY_BASE 0x70UL -#define HC_INITIALIZE_TRUSTY _HC_ID(HC_ID, HC_ID_TRUSTY_BASE + 0x00) -#define HC_WORLD_SWITCH _HC_ID(HC_ID, HC_ID_TRUSTY_BASE + 0x01) -#define HC_GET_SEC_INFO _HC_ID(HC_ID, HC_ID_TRUSTY_BASE + 0x02) +#define HC_INITIALIZE_TRUSTY _HC_ID(HC_ID, HC_ID_TRUSTY_BASE + 0x00UL) +#define HC_WORLD_SWITCH _HC_ID(HC_ID, HC_ID_TRUSTY_BASE + 0x01UL) +#define HC_GET_SEC_INFO _HC_ID(HC_ID, HC_ID_TRUSTY_BASE + 0x02UL) /* Power management */ #define HC_ID_PM_BASE 0x80UL -#define HC_PM_GET_CPU_STATE _HC_ID(HC_ID, HC_ID_PM_BASE + 0x00) +#define HC_PM_GET_CPU_STATE _HC_ID(HC_ID, HC_ID_PM_BASE + 0x00UL) #define ACRN_DOM0_VMID (0UL) #define ACRN_INVALID_VMID (-1) #define ACRN_INVALID_HPA (-1UL) /* Generic memory attributes */ -#define MEM_ACCESS_READ 0x00000001 -#define MEM_ACCESS_WRITE 0x00000002 -#define MEM_ACCESS_EXEC 0x00000004 +#define MEM_ACCESS_READ 0x00000001U +#define MEM_ACCESS_WRITE 0x00000002U +#define MEM_ACCESS_EXEC 0x00000004U #define MEM_ACCESS_RWX (MEM_ACCESS_READ | MEM_ACCESS_WRITE | \ MEM_ACCESS_EXEC) -#define MEM_ACCESS_RIGHT_MASK 0x00000007 -#define MEM_TYPE_WB 0x00000040 -#define MEM_TYPE_WT 0x00000080 -#define MEM_TYPE_UC 0x00000100 -#define MEM_TYPE_WC 0x00000200 -#define MEM_TYPE_WP 0x00000400 -#define MEM_TYPE_MASK 0x000007C0 +#define MEM_ACCESS_RIGHT_MASK 0x00000007U +#define MEM_TYPE_WB 0x00000040U +#define MEM_TYPE_WT 0x00000080U +#define MEM_TYPE_UC 0x00000100U +#define MEM_TYPE_WC 0x00000200U +#define MEM_TYPE_WP 0x00000400U +#define MEM_TYPE_MASK 0x000007C0U /** * @brief Hypercall diff --git a/hypervisor/lib/memory.c b/hypervisor/lib/memory.c index fa50c4a5a..d1450eda1 100644 --- a/hypervisor/lib/memory.c +++ b/hypervisor/lib/memory.c @@ -79,7 +79,7 @@ static void *allocate_mem(struct mem_pool *pool, unsigned int num_bytes) for (bit_idx = ffz64(pool->bitmap[idx]); bit_idx < BITMAP_WORD_SIZE; bit_idx++) { /* Check if selected buffer is free */ - if ((pool->bitmap[idx] & (1 << bit_idx)) != 0U) + if ((pool->bitmap[idx] & (1U << bit_idx)) != 0U) continue; /* Declare temporary variables to be used locally in @@ -105,7 +105,7 @@ static void *allocate_mem(struct mem_pool *pool, unsigned int num_bytes) } /* Break if selected buffer is not free */ - if ((pool->bitmap[tmp_idx] & (1 << tmp_bit_idx)) != 0U) + if ((pool->bitmap[tmp_idx] & (1U << tmp_bit_idx)) != 0U) break; } @@ -128,7 +128,7 @@ static void *allocate_mem(struct mem_pool *pool, unsigned int num_bytes) /* Set allocation bit in bitmap for * this buffer */ - pool->bitmap[idx] |= (1 << bit_idx); + pool->bitmap[idx] |= (1U << bit_idx); /* Set contiguity information for this * buffer in contiguity-bitmap @@ -140,7 +140,7 @@ static void *allocate_mem(struct mem_pool *pool, unsigned int num_bytes) * buffers array */ pool->contiguity_bitmap[idx] |= - (1 << bit_idx); + (1U << bit_idx); } else { /* Set contiguity bit to 0 if * this buffer is not the last @@ -148,7 +148,7 @@ static void *allocate_mem(struct mem_pool *pool, unsigned int num_bytes) * buffers array */ pool->contiguity_bitmap[idx] &= - ~(1 << bit_idx); + ~(1U << bit_idx); } /* Check if bit_idx is out-of-range */ @@ -201,14 +201,14 @@ static void deallocate_mem(struct mem_pool *pool, void *ptr) contiguity_bitmask = &pool->contiguity_bitmap[bmp_idx]; /* Mark the buffer as free */ - if ((*bitmask & (1 << bit_idx)) != 0U) - *bitmask ^= (1 << bit_idx); + if ((*bitmask & (1U << bit_idx)) != 0U) + *bitmask ^= (1U << bit_idx); else break; /* Reset the Contiguity bit of buffer */ - if ((*contiguity_bitmask & (1 << bit_idx)) != 0U) - *contiguity_bitmask ^= (1 << bit_idx); + if ((*contiguity_bitmask & (1U << bit_idx)) != 0U) + *contiguity_bitmask ^= (1U << bit_idx); else break; @@ -372,7 +372,7 @@ void *memcpy_s(void *d, size_t dmax, const void *s, size_t slen) /*make sure 8bytes-aligned for at least one addr.*/ if ((!MEM_ALIGNED_CHECK(src8, 8)) && (!MEM_ALIGNED_CHECK(dest8, 8))) { - for (; slen != 0U && (((uint64_t)src8) & 7) != 0; slen--) + for (; slen != 0U && (((uint64_t)src8) & 7UL) != 0UL; slen--) *dest8++ = *src8++; } @@ -410,7 +410,7 @@ void *memset(void *base, uint8_t v, size_t n) /*do the few bytes to get uint64_t alignment*/ count = n; - for (; count != 0U && ((uint64_t)dest_p & 7) != 0U; count--) + for (; count != 0U && ((uint64_t)dest_p & 7UL) != 0UL; count--) *dest_p++ = v; /*64-bit mode*/ diff --git a/hypervisor/lib/sprintf.c b/hypervisor/lib/sprintf.c index 80db0927c..1a11dae02 100644 --- a/hypervisor/lib/sprintf.c +++ b/hypervisor/lib/sprintf.c @@ -13,37 +13,37 @@ #define PRINT_STRING_MAX_LEN 4096 /** Use upper case letters for hexadecimal format. */ -#define PRINT_FLAG_UPPER 0x00000001 +#define PRINT_FLAG_UPPER 0x00000001U /** Use alternate form. */ -#define PRINT_FLAG_ALTERNATE_FORM 0x00000002 +#define PRINT_FLAG_ALTERNATE_FORM 0x00000002U /** Use '0' instead of ' ' for padding. */ -#define PRINT_FLAG_PAD_ZERO 0x00000004 +#define PRINT_FLAG_PAD_ZERO 0x00000004U /** Use left instead of right justification. */ -#define PRINT_FLAG_LEFT_JUSTIFY 0x00000008 +#define PRINT_FLAG_LEFT_JUSTIFY 0x00000008U /** Always use the sign as prefix. */ -#define PRINT_FLAG_SIGN 0x00000010 +#define PRINT_FLAG_SIGN 0x00000010U /** Use ' ' as prefix if no sign is used. */ -#define PRINT_FLAG_SPACE 0x00000020 +#define PRINT_FLAG_SPACE 0x00000020U /** The original value was a (unsigned) char. */ -#define PRINT_FLAG_CHAR 0x00000040 +#define PRINT_FLAG_CHAR 0x00000040U /** The original value was a (unsigned) short. */ -#define PRINT_FLAG_SHORT 0x00000080 +#define PRINT_FLAG_SHORT 0x00000080U /** The original value was a (unsigned) long. */ -#define PRINT_FLAG_LONG 0x00000100 +#define PRINT_FLAG_LONG 0x00000100U /** The original value was a (unsigned) long long. */ -#define PRINT_FLAG_LONG_LONG 0x00000200 +#define PRINT_FLAG_LONG_LONG 0x00000200U /** The value is interpreted as unsigned. */ -#define PRINT_FLAG_UINT32 0x00000400 +#define PRINT_FLAG_UINT32 0x00000400U /** Structure used to save (v)snprintf() specific values */ struct snprint_param { diff --git a/hypervisor/lib/string.c b/hypervisor/lib/string.c index ad866324d..226027054 100644 --- a/hypervisor/lib/string.c +++ b/hypervisor/lib/string.c @@ -102,7 +102,7 @@ const uint16_t _sch_istable[256] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -#define _sch_test(c, bit) (_sch_istable[(c) & 0xff] & (uint16_t)(bit)) +#define _sch_test(c, bit) (_sch_istable[(c) & 0xffU] & (uint16_t)(bit)) #define ISALPHA(c) _sch_test(c, _sch_isalpha) #define ISALNUM(c) _sch_test(c, _sch_isalnum) @@ -185,11 +185,11 @@ const uint8_t _sch_toupper[256] = { 248, 249, 250, 251, 252, 253, 254, 255, }; -#define TOUPPER(c) _sch_toupper[(c) & 0xff] -#define TOLOWER(c) _sch_tolower[(c) & 0xff] +#define TOUPPER(c) _sch_toupper[(c) & 0xffU] +#define TOLOWER(c) _sch_tolower[(c) & 0xffU] #ifndef ULONG_MAX -#define ULONG_MAX ((uint64_t)(~0L)) /* 0xFFFFFFFF */ +#define ULONG_MAX ((uint64_t)(~0UL)) /* 0xFFFFFFFF */ #endif #ifndef LONG_MAX @@ -558,7 +558,7 @@ char hexdigit(int decimal_val) '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; /* Return hex character */ - return hexdigits[decimal_val & 0x0F]; + return hexdigits[decimal_val & 0x0FU]; } int strcmp(const char *s1, const char *s2)