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modularization: boot component

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Boot component prepares the very basic platform boot env. It finally call
into platform initilization entries:

- bsp_boot_init & cpu_secondary_init for start up
- or restore_s3_context for wakeup

this patch is the final one, it did some code clean up and move some definition
from vm0_boot.h to boot_context.h.

after this patch, the boot component include files:
arch/x86/boot/cpu_primary.S
arch/x86/boot/trampoline.S
arch/x86/boot/cpu_save_boot_ctx.S
arch/x86/boot/idt.S
boot/reloc.c
boot/include/reloc.h
include/arch/x86/boot/idt.h
include/arch/x86/boot/boot_context.h

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
Jason Chen CJ
2018-11-30 20:20:06 +08:00
committed by wenlingz
parent b54f23316a
commit aa9af27338
10 changed files with 68 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
hypervisor/include/arch/x86/boot/boot_context.h Normal file
View File

@@ -0,0 +1,51 @@
/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BOOT_CTX_H
#define BOOT_CTX_H
#ifdef ASSEMBLER
#define BOOT_CTX_CR0_OFFSET 176
#define BOOT_CTX_CR3_OFFSET 192
#define BOOT_CTX_CR4_OFFSET 184
#define BOOT_CTX_IDT_OFFSET 144
#define BOOT_CTX_GDT_OFFSET 128
#define BOOT_CTX_LDT_SEL_OFFSET 280
#define BOOT_CTX_TR_SEL_OFFSET 282
#define BOOT_CTX_CS_SEL_OFFSET 268
#define BOOT_CTX_SS_SEL_OFFSET 270
#define BOOT_CTX_DS_SEL_OFFSET 272
#define BOOT_CTX_ES_SEL_OFFSET 274
#define BOOT_CTX_FS_SEL_OFFSET 276
#define BOOT_CTX_GS_SEL_OFFSET 278
#define BOOT_CTX_CS_AR_OFFSET 248
#define BOOT_CTX_CS_LIMIT_OFFSET 252
#define BOOT_CTX_EFER_LOW_OFFSET 200
#define BOOT_CTX_EFER_HIGH_OFFSET 204
#define SIZE_OF_BOOT_CTX 296
#else
#define BOOT_CTX_CR0_OFFSET 176U
#define BOOT_CTX_CR3_OFFSET 192U
#define BOOT_CTX_CR4_OFFSET 184U
#define BOOT_CTX_IDT_OFFSET 144U
#define BOOT_CTX_GDT_OFFSET 128U
#define BOOT_CTX_LDT_SEL_OFFSET 280U
#define BOOT_CTX_TR_SEL_OFFSET 282U
#define BOOT_CTX_CS_SEL_OFFSET 268U
#define BOOT_CTX_SS_SEL_OFFSET 270U
#define BOOT_CTX_DS_SEL_OFFSET 272U
#define BOOT_CTX_ES_SEL_OFFSET 274U
#define BOOT_CTX_FS_SEL_OFFSET 276U
#define BOOT_CTX_GS_SEL_OFFSET 278U
#define BOOT_CTX_CS_AR_OFFSET 248U
#define BOOT_CTX_CS_LIMIT_OFFSET 252U
#define BOOT_CTX_EFER_LOW_OFFSET 200U
#define BOOT_CTX_EFER_HIGH_OFFSET 204U
#define SIZE_OF_BOOT_CTX 296U
struct acrn_vcpu_regs;
extern struct acrn_vcpu_regs boot_context;
#endif /* ASSEMBLER */
#endif /* BOOT_CTX_H */

1
hypervisor/include/arch/x86/guest/guest.h
View File

@@ -220,7 +220,6 @@ int copy_from_gva(struct acrn_vcpu *vcpu, void *h_ptr, uint64_t gva,
*/
int copy_to_gva(struct acrn_vcpu *vcpu, void *h_ptr, uint64_t gva,
uint32_t size, uint32_t *err_code, uint64_t *fault_addr);
extern struct acrn_vcpu_regs vm0_boot_context;
/**
* @}
*/

41
hypervisor/include/arch/x86/guest/vm0_boot.h
View File

@@ -7,45 +7,6 @@
#ifndef VM0_BOOT_H
#define VM0_BOOT_H
#ifdef ASSEMBLER
#define BOOT_CTX_CR0_OFFSET 176
#define BOOT_CTX_CR3_OFFSET 192
#define BOOT_CTX_CR4_OFFSET 184
#define BOOT_CTX_IDT_OFFSET 144
#define BOOT_CTX_GDT_OFFSET 128
#define BOOT_CTX_LDT_SEL_OFFSET 280
#define BOOT_CTX_TR_SEL_OFFSET 282
#define BOOT_CTX_CS_SEL_OFFSET 268
#define BOOT_CTX_SS_SEL_OFFSET 270
#define BOOT_CTX_DS_SEL_OFFSET 272
#define BOOT_CTX_ES_SEL_OFFSET 274
#define BOOT_CTX_FS_SEL_OFFSET 276
#define BOOT_CTX_GS_SEL_OFFSET 278
#define BOOT_CTX_CS_AR_OFFSET 248
#define BOOT_CTX_CS_LIMIT_OFFSET 252
#define BOOT_CTX_EFER_LOW_OFFSET 200
#define BOOT_CTX_EFER_HIGH_OFFSET 204
#define SIZE_OF_BOOT_CTX 296
#else
#define BOOT_CTX_CR0_OFFSET 176U
#define BOOT_CTX_CR3_OFFSET 192U
#define BOOT_CTX_CR4_OFFSET 184U
#define BOOT_CTX_IDT_OFFSET 144U
#define BOOT_CTX_GDT_OFFSET 128U
#define BOOT_CTX_LDT_SEL_OFFSET 280U
#define BOOT_CTX_TR_SEL_OFFSET 282U
#define BOOT_CTX_CS_SEL_OFFSET 268U
#define BOOT_CTX_SS_SEL_OFFSET 270U
#define BOOT_CTX_DS_SEL_OFFSET 272U
#define BOOT_CTX_ES_SEL_OFFSET 274U
#define BOOT_CTX_FS_SEL_OFFSET 276U
#define BOOT_CTX_GS_SEL_OFFSET 278U
#define BOOT_CTX_CS_AR_OFFSET 248U
#define BOOT_CTX_CS_LIMIT_OFFSET 252U
#define BOOT_CTX_EFER_LOW_OFFSET 200U
#define BOOT_CTX_EFER_HIGH_OFFSET 204U
#define SIZE_OF_BOOT_CTX 296U
#ifdef CONFIG_EFI_STUB
struct efi_context {
struct acrn_vcpu_regs vcpu_regs;
@@ -56,5 +17,5 @@ struct efi_context {
void *get_rsdp_from_uefi(void);
void *get_ap_trampoline_buf(void);
#endif
#endif /* ASSEMBLER */
#endif /* VM0_BOOT_H */