acrn-config: update vm configurations for hybrid_rt

update vm configurations for hybrid_rt scenario on WHL/EHL/TGL/CFL
boards, add 1 YaaG and assign 1 more pcpu for WaaG.

Tracked-On: #5390

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Shuang Zheng 2020-10-14 04:03:01 +00:00 committed by wenlingz
parent 13d39fda85
commit abcfc1c0a0
11 changed files with 36 additions and 15 deletions

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@ -18,8 +18,8 @@ VM_NUM_MAP_TOTAL_HV_RAM_SIZE = {
2:0x7800000,
# 150M
3:0x9600000,
# 180M
4:0xB400000,
# 190M
4:0xBE00000,
# 210M
5:0xD200000,
# 250M

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@ -2,7 +2,7 @@
CONFIG_BOARD="cfl-k700-i7"
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x9800000
CONFIG_HV_RAM_SIZE=0xc000000
CONFIG_PLATFORM_RAM_SIZE=0x800000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_SOS_RAM_SIZE=0x800000000

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@ -21,12 +21,13 @@
"no_timer_check " \
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000 " \
"maxcpus=2"
"maxcpus=6"
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(6U) | AFFINITY_CPU(7U))
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U))
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U) | AFFINITY_CPU(4U) | AFFINITY_CPU(5U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(4U) | AFFINITY_CPU(5U))
#ifdef CONFIG_RDT_ENABLED

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@ -2,7 +2,7 @@
CONFIG_BOARD="ehl-crb-b"
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x9800000
CONFIG_HV_RAM_SIZE=0xc000000
CONFIG_PLATFORM_RAM_SIZE=0x400000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_SOS_RAM_SIZE=0x400000000

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@ -28,7 +28,8 @@
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U))
#ifdef CONFIG_RDT_ENABLED
@ -71,7 +72,8 @@
#define VM0_VCPU_CLOS {0U}
#define VM1_VCPU_CLOS {0U}
#define VM2_VCPU_CLOS {0U}
#define VM2_VCPU_CLOS {0U, 0U}
#define VM3_VCPU_CLOS {0U}
#endif
#define VM0_CONFIG_PCI_DEV_NUM 4U

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@ -121,4 +121,20 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.addr.port_base = INVALID_COM_BASE,
},
},
{ /* VM3 */
CONFIG_POST_STD_VM(2),
#ifdef CONFIG_RDT_ENABLED
.clos = VM3_VCPU_CLOS,
#endif
.cpu_affinity = VM3_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
},
};

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@ -15,7 +15,7 @@
*/
#define PRE_VM_NUM 1U
#define SOS_VM_NUM 1U
#define MAX_POST_VM_NUM 1U
#define MAX_POST_VM_NUM 2U
#define CONFIG_MAX_KATA_VM_NUM 0U
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */

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@ -29,7 +29,8 @@
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U))
#ifdef CONFIG_RDT_ENABLED

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@ -2,7 +2,7 @@
CONFIG_BOARD="whl-ipc-i5"
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x9800000
CONFIG_HV_RAM_SIZE=0xc000000
CONFIG_PLATFORM_RAM_SIZE=0x400000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_SOS_RAM_SIZE=0x400000000

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@ -29,7 +29,8 @@
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U))
#ifdef CONFIG_RDT_ENABLED

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@ -2,7 +2,7 @@
CONFIG_BOARD="whl-ipc-i7"
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x9800000
CONFIG_HV_RAM_SIZE=0xc000000
CONFIG_PLATFORM_RAM_SIZE=0x400000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_SOS_RAM_SIZE=0x400000000