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HV: Fix missing brackets for MISRA C Violations

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Patch 6 of 7.
Added changes to make sure Misra C violations are fixed
for rules 11S and 12S.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
This commit is contained in:
Arindam Roy
2018-07-12 15:02:55 -07:00
committed by wenlingz
parent 4aa6cdacf7
commit af806a93bd
17 changed files with 200 additions and 111 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
hypervisor/include/arch/x86/io.h
View File

@@ -63,20 +63,23 @@ static inline uint32_t io_read_long(uint16_t port)
static inline void io_write(uint32_t v, uint16_t addr, size_t sz)
{
if (sz == 1U)
if (sz == 1U) {
io_write_byte((uint8_t)v, addr);
else if (sz == 2U)
} else if (sz == 2U) {
io_write_word((uint16_t)v, addr);
else
} else {
io_write_long(v, addr);
}
}
static inline uint32_t io_read(uint16_t addr, size_t sz)
{
if (sz == 1U)
if (sz == 1U) {
return io_read_byte(addr);
if (sz == 2U)
}
if (sz == 2U) {
return io_read_word(addr);
}
return io_read_long(addr);
}

18
hypervisor/include/debug/trace.h
View File

@@ -78,11 +78,13 @@ struct trace_entry {
static inline bool
trace_check(uint16_t cpu_id, __unused uint32_t evid)
{
if (cpu_id >= phys_cpu_num)
if (cpu_id >= phys_cpu_num) {
return false;
}
if (per_cpu(sbuf, cpu_id)[ACRN_TRACE] == NULL)
if (per_cpu(sbuf, cpu_id)[ACRN_TRACE] == NULL) {
return false;
}
return true;
}
@@ -107,8 +109,9 @@ TRACE_2L(uint32_t evid, uint64_t e, uint64_t f)
struct trace_entry entry;
uint16_t cpu_id = get_cpu_id();
if (!trace_check(cpu_id, evid))
if (!trace_check(cpu_id, evid)) {
return;
}
entry.payload.fields_64.e = e;
entry.payload.fields_64.f = f;
@@ -122,8 +125,9 @@ TRACE_4I(uint32_t evid, uint32_t a, uint32_t b, uint32_t c,
struct trace_entry entry;
uint16_t cpu_id = get_cpu_id();
if (!trace_check(cpu_id, evid))
if (!trace_check(cpu_id, evid)) {
return;
}
entry.payload.fields_32.a = a;
entry.payload.fields_32.b = b;
@@ -139,8 +143,9 @@ TRACE_6C(uint32_t evid, uint8_t a1, uint8_t a2, uint8_t a3,
struct trace_entry entry;
uint16_t cpu_id = get_cpu_id();
if (!trace_check(cpu_id, evid))
if (!trace_check(cpu_id, evid)) {
return;
}
entry.payload.fields_8.a1 = a1;
entry.payload.fields_8.a2 = a2;
@@ -162,8 +167,9 @@ TRACE_16STR(uint32_t evid, const char name[])
uint16_t cpu_id = get_cpu_id();
size_t len, i;
if (!trace_check(cpu_id, evid))
if (!trace_check(cpu_id, evid)) {
return;
}
entry.payload.fields_64.e = 0UL;
entry.payload.fields_64.f = 0UL;

17
hypervisor/include/lib/bits.h
View File

@@ -66,8 +66,9 @@
static inline uint16_t fls32(uint32_t value)
{
uint32_t ret = 0U;
if (value == 0U)
if (value == 0U) {
return (INVALID_BIT_INDEX);
}
asm volatile("bsrl %1,%0"
: "=r" (ret)
: "rm" (value));
@@ -77,8 +78,9 @@ static inline uint16_t fls32(uint32_t value)
static inline uint16_t fls64(uint64_t value)
{
uint64_t ret = 0UL;
if (value == 0UL)
if (value == 0UL) {
return (INVALID_BIT_INDEX);
}
asm volatile("bsrq %1,%0"
: "=r" (ret)
: "rm" (value));
@@ -113,8 +115,9 @@ static inline uint16_t fls64(uint64_t value)
static inline uint16_t ffs64(uint64_t value)
{
uint64_t ret = 0UL;
if (value == 0UL)
if (value == 0UL) {
return (INVALID_BIT_INDEX);
}
asm volatile("bsfq %1,%0"
: "=r" (ret)
: "rm" (value));
@@ -144,9 +147,9 @@ static inline uint16_t ffz64(uint64_t value)
*/
static inline uint16_t clz(uint32_t value)
{
if (value == 0U)
if (value == 0U) {
return 32U;
else{
} else {
return (31U - fls32(value));
}
}
@@ -160,9 +163,9 @@ static inline uint16_t clz(uint32_t value)
*/
static inline uint16_t clz64(uint64_t value)
{
if (value == 0UL)
if (value == 0UL) {
return 64U;
else{
} else {
return (63U - fls64(value));
}
}

3
hypervisor/include/lib/list.h
View File

@@ -94,8 +94,9 @@ static inline void __list_splice(struct list_head *list,
static inline void list_splice(struct list_head *list, struct list_head *head)
{
if (!list_empty(list))
if (!list_empty(list)) {
__list_splice(list, head);
}
}
static inline void list_splice_init(struct list_head *list,