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HV: Fix missing brackets for MISRA C Violations

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Patch 6 of 7.
Added changes to make sure Misra C violations are fixed
for rules 11S and 12S.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
This commit is contained in:
Arindam Roy
2018-07-12 15:02:55 -07:00
committed by wenlingz
parent 4aa6cdacf7
commit af806a93bd
17 changed files with 200 additions and 111 deletions
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17
hypervisor/include/lib/bits.h
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@@ -66,8 +66,9 @@
static inline uint16_t fls32(uint32_t value)
{
uint32_t ret = 0U;
if (value == 0U)
if (value == 0U) {
return (INVALID_BIT_INDEX);
}
asm volatile("bsrl %1,%0"
: "=r" (ret)
: "rm" (value));
@@ -77,8 +78,9 @@ static inline uint16_t fls32(uint32_t value)
static inline uint16_t fls64(uint64_t value)
{
uint64_t ret = 0UL;
if (value == 0UL)
if (value == 0UL) {
return (INVALID_BIT_INDEX);
}
asm volatile("bsrq %1,%0"
: "=r" (ret)
: "rm" (value));
@@ -113,8 +115,9 @@ static inline uint16_t fls64(uint64_t value)
static inline uint16_t ffs64(uint64_t value)
{
uint64_t ret = 0UL;
if (value == 0UL)
if (value == 0UL) {
return (INVALID_BIT_INDEX);
}
asm volatile("bsfq %1,%0"
: "=r" (ret)
: "rm" (value));
@@ -144,9 +147,9 @@ static inline uint16_t ffz64(uint64_t value)
*/
static inline uint16_t clz(uint32_t value)
{
if (value == 0U)
if (value == 0U) {
return 32U;
else{
} else {
return (31U - fls32(value));
}
}
@@ -160,9 +163,9 @@ static inline uint16_t clz(uint32_t value)
*/
static inline uint16_t clz64(uint64_t value)
{
if (value == 0UL)
if (value == 0UL) {
return 64U;
else{
} else {
return (63U - fls64(value));
}
}