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https://github.com/projectacrn/acrn-hypervisor.git
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HV: Adding partition mode support for cb2_dnv
Adding partition mode support for cb2_dnv. Tracked-On: #1853 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
dongshen
lijinxia
parent
664bc1bace
commit
b0e1657b4f
@ -300,7 +300,7 @@ config CONSTANT_ACPI
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built-in tables after parsing the real ACPI tables at runtime.
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config DMAR_PARSE_ENABLED
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bool
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bool "Enable DMAR parsing"
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default n if PLATFORM_SBL
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default y if PLATFORM_UEFI
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help
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7
hypervisor/arch/x86/configs/cb2_dnv.config
Normal file
7
hypervisor/arch/x86/configs/cb2_dnv.config
Normal file
@ -0,0 +1,7 @@
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CONFIG_BOARD="cb2_dnv"
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CONFIG_PLATFORM_SBL=y
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CONFIG_PARTITION_MODE=y
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CONFIG_SERIAL_PIO=y
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CONFIG_SERIAL_PIO_BASE=0x1000
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CONFIG_DMAR_PARSE_ENABLED=y
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349
hypervisor/partition/cb2_dnv/mptable.c
Normal file
349
hypervisor/partition/cb2_dnv/mptable.c
Normal file
@ -0,0 +1,349 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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#define MPTABLE_BASE 0xF0000U
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/*
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* floating pointer length + maximum length of configuration table
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* ACRN uses contiguous guest memory from 0xF0000 to place floating pointer
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* structure and config table. Maximum length of config table is 64K. So the
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* maximum length of combined floating pointer and config table can go up to
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* 64K + 16 bytes.Since we are left with only 64K from 0xF0000 to 0x100000(1MB)
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* max length is limited to 64K.
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*/
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#define MPTABLE_MAX_LENGTH 65536U
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#define LAPIC_VERSION 16U
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#define MP_SPECREV 4U
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#define MPFP_SIG "_MP_"
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/* Configuration header defines */
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#define MPCH_SIG "PCMP"
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#define MPCH_OEMID "BHyVe "
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#define MPCH_OEMID_LEN 8U
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#define MPCH_PRODID "Hypervisor "
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#define MPCH_PRODID_LEN 12U
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/* Processor entry defines */
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#define MPEP_SIG_FAMILY 6U
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#define MPEP_SIG_MODEL 26U
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#define MPEP_SIG_STEPPING 5U
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#define MPEP_SIG \
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((MPEP_SIG_FAMILY << 8U) | \
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(MPEP_SIG_MODEL << 4U) | \
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(MPEP_SIG_STEPPING))
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#define MPEP_FEATURES 0xBFEBFBFFU /* XXX Intel i7 */
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/* Number of local intr entries */
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#define MPEII_NUM_LOCAL_IRQ 2U
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/* Bus entry defines */
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#define MPE_NUM_BUSES 2U
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#define MPE_BUSNAME_LEN 6U
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#define MPE_BUSNAME_ISA "ISA "
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#define MPE_BUSNAME_PCI "PCI "
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/* Base table entries */
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#define MPCT_ENTRY_PROCESSOR 0U
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#define MPCT_ENTRY_BUS 1U
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#define MPCT_ENTRY_LOCAL_INT 4U
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#define PROCENTRY_FLAG_EN 0x01U
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#define PROCENTRY_FLAG_BP 0x02U
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#define INTENTRY_TYPE_NMI 1U
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#define INTENTRY_TYPE_EXTINT 3U
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#define INTENTRY_FLAGS_POLARITY_CONFORM 0x0U
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#define INTENTRY_FLAGS_TRIGGER_CONFORM 0x0U
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#define VM1_NUM_CPUS 4U
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#define VM2_NUM_CPUS 4U
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/* MP Floating Pointer Structure */
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struct mpfps {
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uint8_t signature[4];
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uint32_t pap;
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uint8_t length;
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uint8_t spec_rev;
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uint8_t checksum;
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uint8_t config_type;
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uint8_t mpfb2;
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uint8_t mpfb3;
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uint8_t mpfb4;
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uint8_t mpfb5;
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} __attribute__((packed));
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/* MP Configuration Table Header */
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struct mpcth {
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uint8_t signature[4];
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uint16_t base_table_length;
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uint8_t spec_rev;
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uint8_t checksum;
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uint8_t oem_id[8];
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uint8_t product_id[12];
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uint32_t oem_table_pointer;
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uint16_t oem_table_size;
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uint16_t entry_count;
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uint32_t apic_address;
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uint16_t extended_table_length;
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uint8_t extended_table_checksum;
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uint8_t reserved;
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} __attribute__((packed));
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struct proc_entry {
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uint8_t type;
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uint8_t apic_id;
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uint8_t apic_version;
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uint8_t cpu_flags;
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uint32_t cpu_signature;
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uint32_t feature_flags;
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uint32_t reserved1;
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uint32_t reserved2;
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} __attribute__((packed));
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struct bus_entry {
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uint8_t type;
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uint8_t bus_id;
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uint8_t bus_type[6];
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} __attribute__((packed));
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struct int_entry {
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uint8_t type;
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uint8_t int_type;
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uint16_t int_flags;
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uint8_t src_bus_id;
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uint8_t src_bus_irq;
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uint8_t dst_apic_id;
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uint8_t dst_apic_int;
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} __attribute__((packed));
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struct mptable_info {
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struct mpfps mpfp;
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struct mpcth mpch;
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struct bus_entry bus_entry_array[MPE_NUM_BUSES];
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struct int_entry int_entry_array[MPEII_NUM_LOCAL_IRQ];
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struct proc_entry proc_entry_array[];
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};
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struct mptable_info mptable_vm1 = {
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.mpfp = {
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.signature = MPFP_SIG,
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.pap = MPTABLE_BASE + sizeof(struct mpfps),
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.length = 1U,
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.spec_rev = MP_SPECREV,
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},
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.mpch = {
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.signature = MPCH_SIG,
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.spec_rev = MP_SPECREV,
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.oem_id = MPCH_OEMID,
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.product_id = MPCH_PRODID,
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.apic_address = LAPIC_BASE,
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.entry_count = (VM1_NUM_CPUS + MPE_NUM_BUSES \
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+ MPEII_NUM_LOCAL_IRQ),
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.base_table_length = (sizeof(struct mpcth) \
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+ VM1_NUM_CPUS * sizeof(struct proc_entry) \
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+ MPE_NUM_BUSES * sizeof(struct bus_entry) \
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+ MPEII_NUM_LOCAL_IRQ * sizeof(struct int_entry))
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},
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.proc_entry_array = {
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{
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.type = MPCT_ENTRY_PROCESSOR,
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.apic_id = 0U,
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.apic_version = LAPIC_VERSION,
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.cpu_flags = PROCENTRY_FLAG_EN | PROCENTRY_FLAG_BP,
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.cpu_signature = MPEP_SIG,
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.feature_flags = MPEP_FEATURES
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},
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{
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.type = MPCT_ENTRY_PROCESSOR,
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.apic_id = 8U,
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.apic_version = LAPIC_VERSION,
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.cpu_flags = PROCENTRY_FLAG_EN,
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.cpu_signature = MPEP_SIG,
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.feature_flags = MPEP_FEATURES,
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},
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{
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.type = MPCT_ENTRY_PROCESSOR,
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.apic_id = 16U,
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.apic_version = LAPIC_VERSION,
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.cpu_flags = PROCENTRY_FLAG_EN,
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.cpu_signature = MPEP_SIG,
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.feature_flags = MPEP_FEATURES,
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},
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{
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.type = MPCT_ENTRY_PROCESSOR,
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.apic_id = 24U,
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.apic_version = LAPIC_VERSION,
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.cpu_flags = PROCENTRY_FLAG_EN,
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.cpu_signature = MPEP_SIG,
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.feature_flags = MPEP_FEATURES,
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}
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},
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.bus_entry_array = {
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{
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.type = MPCT_ENTRY_BUS,
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.bus_id = 0U,
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.bus_type = MPE_BUSNAME_PCI,
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},
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{
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.type = MPCT_ENTRY_BUS,
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.bus_id = 1U,
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.bus_type = MPE_BUSNAME_ISA,
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},
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},
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.int_entry_array = {
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{
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.type = MPCT_ENTRY_LOCAL_INT,
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.int_type = INTENTRY_TYPE_EXTINT,
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.int_flags = INTENTRY_FLAGS_POLARITY_CONFORM \
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| INTENTRY_FLAGS_TRIGGER_CONFORM,
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.dst_apic_id = 0xFFU,
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.dst_apic_int = 0U,
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},
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{
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.type = MPCT_ENTRY_LOCAL_INT,
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.int_type = INTENTRY_TYPE_NMI,
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.int_flags = INTENTRY_FLAGS_POLARITY_CONFORM \
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| INTENTRY_FLAGS_TRIGGER_CONFORM,
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.dst_apic_id = 0xFFU,
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.dst_apic_int = 1U,
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},
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},
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};
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struct mptable_info mptable_vm2 = {
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.mpfp = {
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.signature = MPFP_SIG,
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.pap = MPTABLE_BASE + sizeof(struct mpfps),
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.length = 1U,
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.spec_rev = MP_SPECREV,
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},
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.mpch = {
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.signature = MPCH_SIG,
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.spec_rev = MP_SPECREV,
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.oem_id = MPCH_OEMID,
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.product_id = MPCH_PRODID,
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.apic_address = LAPIC_BASE,
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.entry_count = (VM2_NUM_CPUS + MPE_NUM_BUSES \
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+ MPEII_NUM_LOCAL_IRQ),
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.base_table_length = (sizeof(struct mpcth) \
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+ VM2_NUM_CPUS * sizeof(struct proc_entry) \
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+ MPE_NUM_BUSES * sizeof(struct bus_entry) \
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+ MPEII_NUM_LOCAL_IRQ * sizeof(struct int_entry))
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},
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.proc_entry_array = {
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{
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.type = MPCT_ENTRY_PROCESSOR,
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.apic_id = 28U,
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.apic_version = LAPIC_VERSION,
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.cpu_flags = PROCENTRY_FLAG_EN | PROCENTRY_FLAG_BP,
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.cpu_signature = MPEP_SIG,
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.feature_flags = MPEP_FEATURES
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},
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{
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.type = MPCT_ENTRY_PROCESSOR,
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.apic_id = 20U,
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.apic_version = LAPIC_VERSION,
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.cpu_flags = PROCENTRY_FLAG_EN,
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.cpu_signature = MPEP_SIG,
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.feature_flags = MPEP_FEATURES,
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},
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{
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.type = MPCT_ENTRY_PROCESSOR,
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.apic_id = 12U,
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.apic_version = LAPIC_VERSION,
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.cpu_flags = PROCENTRY_FLAG_EN ,
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.cpu_signature = MPEP_SIG,
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.feature_flags = MPEP_FEATURES
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},
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{
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.type = MPCT_ENTRY_PROCESSOR,
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.apic_id = 4U,
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.apic_version = LAPIC_VERSION,
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.cpu_flags = PROCENTRY_FLAG_EN,
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.cpu_signature = MPEP_SIG,
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.feature_flags = MPEP_FEATURES,
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}
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},
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.bus_entry_array = {
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{
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.type = MPCT_ENTRY_BUS,
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.bus_id = 0U,
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.bus_type = MPE_BUSNAME_PCI,
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},
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{
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.type = MPCT_ENTRY_BUS,
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.bus_id = 1U,
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.bus_type = MPE_BUSNAME_ISA,
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},
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},
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.int_entry_array = {
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{
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.type = MPCT_ENTRY_LOCAL_INT,
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.int_type = INTENTRY_TYPE_EXTINT,
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.int_flags = INTENTRY_FLAGS_POLARITY_CONFORM \
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| INTENTRY_FLAGS_TRIGGER_CONFORM,
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.dst_apic_id = 0xFFU,
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.dst_apic_int = 0U,
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},
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{
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.type = MPCT_ENTRY_LOCAL_INT,
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.int_type = INTENTRY_TYPE_NMI,
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.int_flags = INTENTRY_FLAGS_POLARITY_CONFORM \
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| INTENTRY_FLAGS_TRIGGER_CONFORM,
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.dst_apic_id = 0xFFU,
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.dst_apic_int = 1U,
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},
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},
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};
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static uint8_t mpt_compute_checksum(void *base, size_t len)
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{
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uint8_t *bytes;
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uint8_t sum;
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size_t length = len;
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for (bytes = base, sum = 0U; length > 0U; length--) {
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sum += *bytes;
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bytes++;
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}
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return (256U - sum);
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}
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int mptable_build(struct acrn_vm *vm)
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{
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char *startaddr;
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char *curraddr;
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struct mpcth *mpch;
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struct mpfps *mpfp;
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size_t mptable_length, table_length;
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startaddr = (char *)gpa2hva(vm, MPTABLE_BASE);
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table_length = vm->vm_desc->mptable->mpch.base_table_length;
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mptable_length = sizeof(struct mpfps) + table_length;
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/* Copy mptable info into guest memory */
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(void)memcpy_s((void *)startaddr, MPTABLE_MAX_LENGTH,
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(void *)vm->vm_desc->mptable,
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mptable_length);
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curraddr = startaddr;
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mpfp = (struct mpfps *)curraddr;
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mpfp->checksum = mpt_compute_checksum(mpfp, sizeof(struct mpfps));
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curraddr += sizeof(struct mpfps);
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mpch = (struct mpcth *)curraddr;
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mpch->checksum = mpt_compute_checksum(mpch, mpch->base_table_length);
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return 0U;
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}
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291
hypervisor/partition/cb2_dnv/vm_description.c
Normal file
291
hypervisor/partition/cb2_dnv/vm_description.c
Normal file
@ -0,0 +1,291 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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#define NUM_USER_VMS 2U
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/* Number of CPUs in VM1*/
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#define VM1_NUM_CPUS 4U
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/* Logical CPU IDs assigned to this VM */
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uint16_t VM1_CPUS[VM1_NUM_CPUS] = {0U, 2U, 4U, 6U};
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/* Number of CPUs in VM2*/
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#define VM2_NUM_CPUS 4U
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/* Logical CPU IDs assigned with this VM */
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uint16_t VM2_CPUS[VM2_NUM_CPUS] = {7U, 5U, 3U, 1U};
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static struct vpci_vdev_array vpci_vdev_array1 = {
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.num_pci_vdev = 3,
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.vpci_vdev_list = {
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{/*vdev 0: hostbridge */
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.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
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.ops = &pci_ops_vdev_hostbridge,
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.bar = {},
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.pdev = {
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.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
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}
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},
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{/*vdev 1: Ethernet*/
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.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
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.ops = &pci_ops_vdev_pt,
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.bar = {
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[0] = {
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.base = 0UL,
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.size = 0x200000UL,
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.type = PCIBAR_MEM32,
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},
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[4] = {
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.base = 0UL,
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.size = 0x4000UL,
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.type = PCIBAR_MEM32,
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},
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},
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.pdev = {
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.bdf.bits = {.b = 0x03U, .d = 0x00U, .f = 0x1U},
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.bar = {
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[0] = {
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.base = 0x80C00000,
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.size = 0x200000UL,
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.type = PCIBAR_MEM32,
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},
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[4] = {
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.base = 0x81000000,
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.size = 0x4000UL,
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.type = PCIBAR_MEM32,
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},
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}
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}
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},
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{/*vdev 2: USB*/
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.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x0U},
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.ops = &pci_ops_vdev_pt,
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.bar = {
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[0] = {
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.base = 0UL,
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.size = 0x10000UL,
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.type = PCIBAR_MEM32,
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}
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},
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.pdev = {
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.bdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x0U},
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.bar = {
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[0] = {
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.base = 0x81340000,
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.size = 0x10000UL,
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.type = PCIBAR_MEM32,
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}
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}
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}
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},
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}
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};
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static struct vpci_vdev_array vpci_vdev_array2 = {
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.num_pci_vdev = 3,
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.vpci_vdev_list = {
|
||||
{/*vdev 0: hostbridge*/
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
|
||||
.ops = &pci_ops_vdev_hostbridge,
|
||||
.bar = {},
|
||||
.pdev = {
|
||||
.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
|
||||
}
|
||||
},
|
||||
|
||||
{/*vdev 1: SATA controller*/
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x05U, .f = 0x0U},
|
||||
.ops = &pci_ops_vdev_pt,
|
||||
.bar = {
|
||||
[0] = {
|
||||
.base = 0UL,
|
||||
.size = 0x2000UL,
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
[1] = {
|
||||
.base = 0UL,
|
||||
.size = 0x1000UL,
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
[5] = {
|
||||
.base = 0UL,
|
||||
.size = 0x1000UL,
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
},
|
||||
.pdev = {
|
||||
.bdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x0U},
|
||||
.bar = {
|
||||
[0] = {
|
||||
.base = 0x81354000,
|
||||
.size = 0x2000UL,
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
[1] = {
|
||||
.base = 0x8135f000,
|
||||
.size = 0x1000UL,
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
[5] = {
|
||||
.base = 0x8135e000,
|
||||
.size = 0x1000UL,
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
}
|
||||
}
|
||||
},
|
||||
|
||||
{/*vdev 2: Ethernet*/
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x06U, .f = 0x0U},
|
||||
.ops = &pci_ops_vdev_pt,
|
||||
.bar = {
|
||||
[0] = {
|
||||
.base = 0UL,
|
||||
.size = 0x200000UL,
|
||||
.type = PCIBAR_MEM32,
|
||||
},
|
||||
[4] = {
|
||||
.base = 0UL,
|
||||
.size = 0x4000UL,
|
||||
.type = PCIBAR_MEM32,
|
||||
},
|
||||
},
|
||||
|
||||
.pdev = {
|
||||
.bdf.bits = {.b = 0x03U, .d = 0x00U, .f = 0x0U},
|
||||
.bar = {
|
||||
[0] = {
|
||||
.base = 0x80e00000,
|
||||
.size = 0x200000UL,
|
||||
.type = PCIBAR_MEM32,
|
||||
},
|
||||
[4] = {
|
||||
.base = 0x81004000,
|
||||
.size = 0x4000UL,
|
||||
.type = PCIBAR_MEM32,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
},
|
||||
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************/
|
||||
/* User Defined VM definitions */
|
||||
/*******************************/
|
||||
struct vm_description_array vm_desc_partition = {
|
||||
/* Number of user virtual machines */
|
||||
.num_vm_desc = NUM_USER_VMS,
|
||||
|
||||
/* Virtual Machine descriptions */
|
||||
.vm_desc_array = {
|
||||
{
|
||||
/* Internal variable, MUSTBE init to -1 */
|
||||
.vm_hw_num_cores = VM1_NUM_CPUS,
|
||||
.vm_pcpu_ids = &VM1_CPUS[0],
|
||||
.vm_id = 1U,
|
||||
.start_hpa = 0x100000000UL,
|
||||
.mem_size = 0x80000000UL, /* uses contiguous memory from host */
|
||||
.vm_vuart = true,
|
||||
.bootargs = "root=/dev/sda rw rootwait noxsave maxcpus=4 nohpet console=hvc0 " \
|
||||
"console=ttyS0 no_timer_check ignore_loglevel log_buf_len=16M "\
|
||||
"consoleblank=0 tsc=reliable xapic_phys apic_debug",
|
||||
.vpci_vdev_array = &vpci_vdev_array1,
|
||||
.mptable = &mptable_vm1,
|
||||
.lapic_pt = true,
|
||||
},
|
||||
|
||||
{
|
||||
/* Internal variable, MUSTBE init to -1 */
|
||||
.vm_hw_num_cores = VM2_NUM_CPUS,
|
||||
.vm_pcpu_ids = &VM2_CPUS[0],
|
||||
.vm_id = 2U,
|
||||
.start_hpa = 0x180000000UL,
|
||||
.mem_size = 0x80000000UL, /* uses contiguous memory from host */
|
||||
.vm_vuart = true,
|
||||
.bootargs = "root=/dev/sda2 rw rootwait noxsave maxcpus=4 nohpet console=hvc0 "\
|
||||
"console=ttyS0 no_timer_check ignore_loglevel log_buf_len=16M "\
|
||||
"consoleblank=0 tsc=reliable xapic_phys apic_debug",
|
||||
.vpci_vdev_array = &vpci_vdev_array2,
|
||||
.mptable = &mptable_vm2,
|
||||
.lapic_pt = true,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
const struct pcpu_vm_desc_mapping pcpu_vm_desc_map[] = {
|
||||
{
|
||||
.vm_desc_ptr = &vm_desc_partition.vm_desc_array[0],
|
||||
.is_bsp = true,
|
||||
},
|
||||
{
|
||||
.vm_desc_ptr = &vm_desc_partition.vm_desc_array[1],
|
||||
.is_bsp = false,
|
||||
},
|
||||
{
|
||||
.vm_desc_ptr = &vm_desc_partition.vm_desc_array[0],
|
||||
.is_bsp = false,
|
||||
},
|
||||
{
|
||||
.vm_desc_ptr = &vm_desc_partition.vm_desc_array[1],
|
||||
.is_bsp = false,
|
||||
},
|
||||
{
|
||||
.vm_desc_ptr = &vm_desc_partition.vm_desc_array[0],
|
||||
.is_bsp = false,
|
||||
},
|
||||
{
|
||||
.vm_desc_ptr = &vm_desc_partition.vm_desc_array[1],
|
||||
.is_bsp = false,
|
||||
},
|
||||
{
|
||||
.vm_desc_ptr = &vm_desc_partition.vm_desc_array[0],
|
||||
.is_bsp = false,
|
||||
},
|
||||
{
|
||||
.vm_desc_ptr = &vm_desc_partition.vm_desc_array[1],
|
||||
.is_bsp = true,
|
||||
},
|
||||
};
|
||||
|
||||
const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
|
||||
{ /* 0 to mptable */
|
||||
.baseaddr = 0x0U,
|
||||
.length = 0xEFFFFU,
|
||||
.type = E820_TYPE_RAM
|
||||
},
|
||||
|
||||
{ /* mptable 65536U */
|
||||
.baseaddr = 0xF0000U,
|
||||
.length = 0x10000U,
|
||||
.type = E820_TYPE_RESERVED
|
||||
},
|
||||
|
||||
{ /* mptable to lowmem */
|
||||
.baseaddr = 0x100000U,
|
||||
.length = 0x7FF00000U,
|
||||
.type = E820_TYPE_RAM
|
||||
},
|
||||
|
||||
{ /* lowmem to PCI hole */
|
||||
.baseaddr = 0x80000000U,
|
||||
.length = 0x40000000U,
|
||||
.type = E820_TYPE_RESERVED
|
||||
},
|
||||
|
||||
{ /* PCI hole to 4G */
|
||||
.baseaddr = 0xe0000000U,
|
||||
.length = 0x20000000U,
|
||||
.type = E820_TYPE_RESERVED
|
||||
},
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user