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hv: nested: Introduce L2 VM EPT VIOLATION handler

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With shadow EPT, the hypervisor walks through guest EPT table:

  * If the entry is not present in guest EPT, ACRN injects EPT_VIOLATION
    to L1 VM and resumes to L1 VM.

  * If the entry is present in guest EPT, do the EPT_MISCONFIG check.
    Inject EPT_MISCONFIG to L1 VM if the check failed.

  * If the entry is present in guest EPT, do permission check.
    Reflect EPT_VIOLATION to L1 VM if the check failed.

  * If the entry is present in guest EPT but shadow EPT entry is not
    present, create the shadow entry and resumes to L2 VM.

  * If the entry is present in guest EPT but the GPA in the entry is
    invalid, injects EPT_VIOLATION to L1 VM and resumes L1 VM.

Tracked-On: #5923
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shuo A Liu
2021-05-27 15:20:12 +08:00
committed by Xie, Nanlin
parent 8565750bbe
commit b10b5658bd
3 changed files with 211 additions and 3 deletions
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12
hypervisor/include/arch/x86/asm/guest/vept.h
View File

@@ -7,6 +7,18 @@
#define VEPT_H
#ifdef CONFIG_NVMX_ENABLED
#define RESERVED_BITS(start, end) (((1UL << (end - start + 1)) - 1) << start)
#define IA32E_PML4E_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(3U, 7U) | RESERVED_BITS(phy_addr_width, 51U))
#define IA32E_PDPTE_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(3U, 6U) | RESERVED_BITS(phy_addr_width, 51U))
#define IA32E_PDPTE_LEAF_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(12U,29U)| RESERVED_BITS(phy_addr_width, 51U))
#define IA32E_PDE_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(3U, 6U) | RESERVED_BITS(phy_addr_width, 51U))
#define IA32E_PDE_LEAF_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(12U,20U)| RESERVED_BITS(phy_addr_width, 51U))
#define IA32E_PTE_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(phy_addr_width, 51U))
#define PAGING_ENTRY_SHIFT(lvl) ((IA32E_PT - (lvl)) * 9U + PTE_SHIFT)
#define PAGING_ENTRY_OFFSET(addr, lvl) (((addr) >> PAGING_ENTRY_SHIFT(lvl)) & (PTRS_PER_PTE - 1UL))
/*
* A descriptor to store info of nested EPT
*/

2
hypervisor/include/arch/x86/asm/pgtable.h
View File

@@ -139,6 +139,8 @@
#define PDPTE_PFN_MASK 0x0000FFFFFFFFF000UL
#define PDE_PFN_MASK 0x0000FFFFFFFFF000UL
#define EPT_ENTRY_PFN_MASK ((~EPT_PFN_HIGH_MASK) & PAGE_MASK)
/**
* @brief Page tables level in IA32 paging mode
*/