From b25a30f271dfb213ef15778356e75acfedbc93e6 Mon Sep 17 00:00:00 2001 From: Jian Jun Chen Date: Fri, 18 May 2018 13:25:25 +0800 Subject: [PATCH] dm: add default handling in pci_emul_capwrite Virtio 1.0 introduced several PCIY_VENDOR capabilities. When trying to write to these capabilities no action is taken so the registers in the capability of VIRTIO_PCI_CAP_PCI_CFG such as bar, offset and length remain the default value 0. Later a read or write of pci_cfg_data needs these information to perform the indirect read or write to the bar region. Signed-off-by: Jian Jun Chen Reviewed-by: Hao Li Reviewed-by: Zhao Yakui Acked-by: Kevin Tian --- devicemodel/hw/pci/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/devicemodel/hw/pci/core.c b/devicemodel/hw/pci/core.c index 49e8da80e..7afba9b4a 100644 --- a/devicemodel/hw/pci/core.c +++ b/devicemodel/hw/pci/core.c @@ -1086,6 +1086,7 @@ pci_emul_capwrite(struct pci_vdev *dev, int offset, int bytes, uint32_t val) pciecap_cfgwrite(dev, capoff, offset, bytes, val); break; default: + CFGWRITE(dev, offset, val, bytes); break; } }