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hv: rename vlapic_pir_desc to pi_desc
Rename struct vlapic_pir_desc to pi_desc Rename struct member and local variable pir_desc to pid pir=posted interrupt request, pi=posted interrupt pid=posted interrupt descriptor pir is part of pi descriptor, so it is better to use pi instead of pir struct pi_desc will be moved to vmx.h in subsequent commit. Tracked-On: #4506 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
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@ -629,7 +629,7 @@ uint64_t apicv_get_pir_desc_paddr(struct acrn_vcpu *vcpu)
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struct acrn_vlapic *vlapic;
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vlapic = &vcpu->arch.vlapic;
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return hva2hpa(&(vlapic->pir_desc));
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return hva2hpa(&(vlapic->pid));
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}
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/**
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@ -1672,7 +1672,7 @@ vlapic_reset(struct acrn_vlapic *vlapic, const struct acrn_apicv_ops *ops, enum
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lapic = &(vlapic->apic_page);
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(void)memset((void *)lapic, 0U, sizeof(struct lapic_regs));
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(void)memset((void *)&(vlapic->pir_desc), 0U, sizeof(vlapic->pir_desc));
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(void)memset((void *)&(vlapic->pid), 0U, sizeof(vlapic->pid));
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if (mode == INIT_RESET) {
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if ((preserved_lapic_mode & APICBASE_ENABLED) != 0U ) {
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@ -2229,16 +2229,16 @@ void vlapic_free(struct acrn_vcpu *vcpu)
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static bool
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apicv_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector)
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{
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struct vlapic_pir_desc *pir_desc;
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struct pi_desc *pid;
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uint32_t idx;
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bool notify = false;
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pir_desc = &(vlapic->pir_desc);
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pid = &(vlapic->pid);
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idx = vector >> 6U;
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if (!bitmap_test_and_set_lock((uint16_t)(vector & 0x3fU), &pir_desc->pir[idx])) {
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notify = (atomic_cmpxchg64(&pir_desc->pending, 0UL, 1UL) == 0UL);
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if (!bitmap_test_and_set_lock((uint16_t)(vector & 0x3fU), &pid->pir[idx])) {
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notify = (atomic_cmpxchg64(&pid->pending, 0UL, 1UL) == 0UL);
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}
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return notify;
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}
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@ -2289,21 +2289,21 @@ static bool apicv_basic_inject_intr(struct acrn_vlapic *vlapic,
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*/
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static void vlapic_apicv_inject_pir(struct acrn_vlapic *vlapic)
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{
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struct vlapic_pir_desc *pir_desc;
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struct pi_desc *pid;
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struct lapic_regs *lapic;
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uint64_t val, pirval;
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uint16_t rvi, pirbase = 0U, i;
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uint16_t intr_status_old, intr_status_new;
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struct lapic_reg *irr = NULL;
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pir_desc = &(vlapic->pir_desc);
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if (atomic_cmpxchg64(&pir_desc->pending, 1UL, 0UL) == 1UL) {
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pid = &(vlapic->pid);
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if (atomic_cmpxchg64(&pid->pending, 1UL, 0UL) == 1UL) {
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pirval = 0UL;
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lapic = &(vlapic->apic_page);
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irr = &lapic->irr[0];
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for (i = 0U; i < 4U; i++) {
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val = atomic_readandclear64(&pir_desc->pir[i]);
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val = atomic_readandclear64(&pid->pir[i]);
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if (val != 0UL) {
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irr[i * 2U].v |= (uint32_t)val;
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irr[(i * 2U) + 1U].v |= (uint32_t)(val >> 32U);
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@ -43,7 +43,9 @@
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#define VLAPIC_MAXLVT_INDEX APIC_LVT_CMCI
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struct vlapic_pir_desc {
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/* Posted Interrupt Descriptor (PID) in VT-d spec */
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struct pi_desc {
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/* Posted Interrupt Requests, one bit per requested vector */
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uint64_t pir[4];
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uint64_t pending;
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uint64_t unused[3];
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@ -58,16 +60,16 @@ struct vlapic_timer {
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struct acrn_vlapic {
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/*
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* Please keep 'apic_page' and 'pir_desc' be the first two fields in
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* Please keep 'apic_page' and 'pid' be the first two fields in
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* current structure, as below alignment restrictions are mandatory
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* to support APICv features:
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* - 'apic_page' MUST be 4KB aligned.
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* - 'pir_desc' MUST be 64 bytes aligned.
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* - 'pid' MUST be 64 bytes aligned.
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* IRR, TMR and PIR could be accessed by other vCPUs when deliver
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* an interrupt to vLAPIC.
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*/
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struct lapic_regs apic_page;
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struct vlapic_pir_desc pir_desc;
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struct pi_desc pid;
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struct acrn_vm *vm;
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struct acrn_vcpu *vcpu;
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