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hv: rename vlapic_pir_desc to pi_desc

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Rename struct vlapic_pir_desc to pi_desc
Rename struct member and local variable pir_desc to pid

pir=posted interrupt request, pi=posted interrupt
pid=posted interrupt descriptor
pir is part of pi descriptor, so it is better to use pi instead of pir

struct pi_desc will be moved to vmx.h in subsequent commit.

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
dongshen 2020-03-18 11:15:26 -07:00 committed by wenlingz
parent e1ae5ba638
commit b384d04ad1
2 changed files with 16 additions and 14 deletions
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20
hypervisor/arch/x86/guest/vlapic.c
View File

@ -629,7 +629,7 @@ uint64_t apicv_get_pir_desc_paddr(struct acrn_vcpu *vcpu)
struct acrn_vlapic *vlapic; struct acrn_vlapic *vlapic;
vlapic = &vcpu->arch.vlapic; vlapic = &vcpu->arch.vlapic;
return hva2hpa(&(vlapic->pir_desc)); return hva2hpa(&(vlapic->pid));
} }
/** /**
@ -1672,7 +1672,7 @@ vlapic_reset(struct acrn_vlapic *vlapic, const struct acrn_apicv_ops *ops, enum
lapic = &(vlapic->apic_page); lapic = &(vlapic->apic_page);
(void)memset((void *)lapic, 0U, sizeof(struct lapic_regs)); (void)memset((void *)lapic, 0U, sizeof(struct lapic_regs));
(void)memset((void *)&(vlapic->pir_desc), 0U, sizeof(vlapic->pir_desc)); (void)memset((void *)&(vlapic->pid), 0U, sizeof(vlapic->pid));
if (mode == INIT_RESET) { if (mode == INIT_RESET) {
if ((preserved_lapic_mode & APICBASE_ENABLED) != 0U ) { if ((preserved_lapic_mode & APICBASE_ENABLED) != 0U ) {
@ -2229,16 +2229,16 @@ void vlapic_free(struct acrn_vcpu *vcpu)
static bool static bool
apicv_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector) apicv_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector)
{ {
struct vlapic_pir_desc *pir_desc; struct pi_desc *pid;
uint32_t idx; uint32_t idx;
bool notify = false; bool notify = false;
pir_desc = &(vlapic->pir_desc); pid = &(vlapic->pid);
idx = vector >> 6U; idx = vector >> 6U;
if (!bitmap_test_and_set_lock((uint16_t)(vector & 0x3fU), &pir_desc->pir[idx])) { if (!bitmap_test_and_set_lock((uint16_t)(vector & 0x3fU), &pid->pir[idx])) {
notify = (atomic_cmpxchg64(&pir_desc->pending, 0UL, 1UL) == 0UL); notify = (atomic_cmpxchg64(&pid->pending, 0UL, 1UL) == 0UL);
} }
return notify; return notify;
} }
@ -2289,21 +2289,21 @@ static bool apicv_basic_inject_intr(struct acrn_vlapic *vlapic,
*/ */
static void vlapic_apicv_inject_pir(struct acrn_vlapic *vlapic) static void vlapic_apicv_inject_pir(struct acrn_vlapic *vlapic)
{ {
struct vlapic_pir_desc *pir_desc; struct pi_desc *pid;
struct lapic_regs *lapic; struct lapic_regs *lapic;
uint64_t val, pirval; uint64_t val, pirval;
uint16_t rvi, pirbase = 0U, i; uint16_t rvi, pirbase = 0U, i;
uint16_t intr_status_old, intr_status_new; uint16_t intr_status_old, intr_status_new;
struct lapic_reg *irr = NULL; struct lapic_reg *irr = NULL;
pir_desc = &(vlapic->pir_desc); pid = &(vlapic->pid);
if (atomic_cmpxchg64(&pir_desc->pending, 1UL, 0UL) == 1UL) { if (atomic_cmpxchg64(&pid->pending, 1UL, 0UL) == 1UL) {
pirval = 0UL; pirval = 0UL;
lapic = &(vlapic->apic_page); lapic = &(vlapic->apic_page);
irr = &lapic->irr[0]; irr = &lapic->irr[0];
for (i = 0U; i < 4U; i++) { for (i = 0U; i < 4U; i++) {
val = atomic_readandclear64(&pir_desc->pir[i]); val = atomic_readandclear64(&pid->pir[i]);
if (val != 0UL) { if (val != 0UL) {
irr[i * 2U].v |= (uint32_t)val; irr[i * 2U].v |= (uint32_t)val;
irr[(i * 2U) + 1U].v |= (uint32_t)(val >> 32U); irr[(i * 2U) + 1U].v |= (uint32_t)(val >> 32U);

10
hypervisor/include/arch/x86/guest/vlapic.h
View File

@ -43,7 +43,9 @@
#define VLAPIC_MAXLVT_INDEX APIC_LVT_CMCI #define VLAPIC_MAXLVT_INDEX APIC_LVT_CMCI
struct vlapic_pir_desc { /* Posted Interrupt Descriptor (PID) in VT-d spec */
struct pi_desc {
/* Posted Interrupt Requests, one bit per requested vector */
uint64_t pir[4]; uint64_t pir[4];
uint64_t pending; uint64_t pending;
uint64_t unused[3]; uint64_t unused[3];
@ -58,16 +60,16 @@ struct vlapic_timer {
struct acrn_vlapic { struct acrn_vlapic {
/* /*
* Please keep 'apic_page' and 'pir_desc' be the first two fields in * Please keep 'apic_page' and 'pid' be the first two fields in
* current structure, as below alignment restrictions are mandatory * current structure, as below alignment restrictions are mandatory
* to support APICv features: * to support APICv features:
* - 'apic_page' MUST be 4KB aligned. * - 'apic_page' MUST be 4KB aligned.
* - 'pir_desc' MUST be 64 bytes aligned. * - 'pid' MUST be 64 bytes aligned.
* IRR, TMR and PIR could be accessed by other vCPUs when deliver * IRR, TMR and PIR could be accessed by other vCPUs when deliver
* an interrupt to vLAPIC. * an interrupt to vLAPIC.
*/ */
struct lapic_regs apic_page; struct lapic_regs apic_page;
struct vlapic_pir_desc pir_desc; struct pi_desc pid;
struct acrn_vm *vm; struct acrn_vm *vm;
struct acrn_vcpu *vcpu; struct acrn_vcpu *vcpu;