hv: riscv: implement virtual exception handling

Add virtual exception handling infrastructure for RISC-V hypervisor
and enables proper virtualization of RISC-V exceptions by allowing
the hypervisor to inject exceptions into guest VS-mode.
- Implement vcpu_set_trap() to inject traps to VS-mode
- Implement vcpu_queue_exception() to queue exceptions for vCPU injection
- Process pending exception requests in riscv_process_vcpu_requests()

v1->v2:
change vcpu_redirect_trap -> vcpu_set_trap

Tracked-On: #8844
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>

hypervisor/include/arch/riscv/asm/guest/vcpu.h

@@ -12,6 +12,8 @@
 
 #ifndef ASSEMBLER
 
+#define RISCV_VCPU_REQUEST_EXCEPTION		0U
+
 struct riscv_vcpu_guest_ctx {
 	uint64_t vsstatus;
 	uint64_t vsie;
@@ -50,6 +52,12 @@ struct riscv_vcpu_host_ctx {
 	uint64_t hip;
 };
 
+struct riscv_vcpu_trap_info {
+	uint64_t epc;
+	uint64_t cause;
+	uint64_t tval;
+};
+
 struct acrn_vcpu_arch {
 	/* This have to be the first member of acrn_vcpu_arch */
 	struct cpu_regs regs;
@@ -57,6 +65,7 @@ struct acrn_vcpu_arch {
 	struct riscv_vcpu_guest_ctx gctx;
 	struct riscv_vcpu_host_ctx hctx;
 
+	struct riscv_vcpu_trap_info trap;
 } __aligned(PAGE_SIZE);
 
 struct acrn_vcpu;

hypervisor/include/arch/riscv/asm/guest/virq.h

@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2025 Intel Corporation.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ARCH_RISCV_GUEST_VIRQ_H
+#define ARCH_RISCV_GUEST_VIRQ_H
+
+void vcpu_set_trap(struct acrn_vcpu *vcpu, struct riscv_vcpu_trap_info *trap);
+void vcpu_queue_exception(struct acrn_vcpu *vcpu, struct riscv_vcpu_trap_info *trap);
+
+#endif /* ARCH_RISCV_GUEST_VIRQ_H */

hypervisor/include/arch/riscv/asm/irq.h

@@ -13,6 +13,7 @@
 #include <cpu.h>
 
 #define IPI_NOTIFY_CPU		0U
+#define EXCEPTION_INVALID	0x7fffffffffffffffUL
 
 /* CPU-local interrupt count (room for standard causes) */
 #define IRQ_NUM_CPU_DOMAIN	16U